JPS6414631A - Analog bus connecting system - Google Patents

Analog bus connecting system

Info

Publication number
JPS6414631A
JPS6414631A JP62168758A JP16875887A JPS6414631A JP S6414631 A JPS6414631 A JP S6414631A JP 62168758 A JP62168758 A JP 62168758A JP 16875887 A JP16875887 A JP 16875887A JP S6414631 A JPS6414631 A JP S6414631A
Authority
JP
Japan
Prior art keywords
bus
analog signal
data
transferred
bits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62168758A
Other languages
Japanese (ja)
Other versions
JP2582077B2 (en
Inventor
Akihiro Katsura
Yoji Nishio
Takeshi Mizumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP62168758A priority Critical patent/JP2582077B2/en
Publication of JPS6414631A publication Critical patent/JPS6414631A/en
Application granted granted Critical
Publication of JP2582077B2 publication Critical patent/JP2582077B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Bus Control (AREA)
  • Dc Digital Transmission (AREA)
  • Dram (AREA)

Abstract

PURPOSE:To decrease the number of pieces of connecting lines for constituting a bus, with regard to a single bus, by providing a D/A converting apparatus and an A/D converter, in a data processor and a memory device, and transmitting an analog signal of a multivalued level onto a signal line of the bus for connecting each of them. CONSTITUTION:In case of executing an information transfer between each of a data processor 10, an input/output device, and a memory device 21, digital information of (n) bits to be transferred is divided into (m) groups, a data of lbits of each group is converted to an analog signal being a signal of a multivalued level by a D/A converter 12, this analog signal is transferred through a bus, and by an A/D converter 22 in a receiving side device, this analog signal is restored to its original digital information. In such a way, for instance, when 4 bits each of a digital data of 32 bits are converted to an analog signal of a multivalued level and transferred, as for the connecting line of the bus, 32 pieces have been required in case of transferring the digital data as it is, but in case when this digital data is converted to an analog data and transferred, 8 pieces will suffice.
JP62168758A 1987-07-08 1987-07-08 Bus connection method Expired - Fee Related JP2582077B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62168758A JP2582077B2 (en) 1987-07-08 1987-07-08 Bus connection method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62168758A JP2582077B2 (en) 1987-07-08 1987-07-08 Bus connection method

Publications (2)

Publication Number Publication Date
JPS6414631A true JPS6414631A (en) 1989-01-18
JP2582077B2 JP2582077B2 (en) 1997-02-19

Family

ID=15873888

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62168758A Expired - Fee Related JP2582077B2 (en) 1987-07-08 1987-07-08 Bus connection method

Country Status (1)

Country Link
JP (1) JP2582077B2 (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04362759A (en) * 1991-06-10 1992-12-15 Sharp Corp Central processing unit
US6266722B1 (en) 1998-07-31 2001-07-24 Mitsubishi Denki Kabushiki Kaisha Multi-value logic device, bus system of multi-value logic devices connected with shared bus, and network system of information processors loaded with multi-value logic devices and connected with shared network
US6317242B1 (en) 1998-01-09 2001-11-13 Fuji Xerox Co., Ltd. Optical bus system and signal processor
US6320590B1 (en) 1998-02-25 2001-11-20 Lg. Philips Lcd Co., Ltd. Data bus compressing apparatus
EP1189142A2 (en) * 2000-08-23 2002-03-20 Infineon Technologies AG Method and apparatus for exchanging data between memories and logic-modules
US6366375B1 (en) 1997-11-10 2002-04-02 Fuji Xerox Co., Ltd. Optical-signal transmission apparatus and method, and signal processing apparatus
US6429838B1 (en) 1998-02-25 2002-08-06 Lg. Philips Lcd Co., Ltd. Correlation modulating apparatus
GB2388000B (en) * 2000-11-15 2005-03-09 Intel Corp Symbol-based signaling for an electromagnetically-coupled bus system
JP2008171393A (en) * 2006-12-14 2008-07-24 Seiko Epson Corp Signal bus, multilevel input interface, and information processor
JP2008306840A (en) * 2007-06-07 2008-12-18 Konica Minolta Holdings Inc Power management system and method of controlling power management system
WO2009084107A1 (en) * 2007-12-28 2009-07-09 Fujitsu Limited Information procesor, access method of information processor and program for making computer perform access method
JP2010061723A (en) * 2008-09-02 2010-03-18 Toppan Printing Co Ltd Semiconductor memory device
JP2013105518A (en) * 2011-11-16 2013-05-30 Samsung Electronics Co Ltd Multi-valued logic device having nonvolatile memory devices
JP2017047816A (en) * 2015-09-03 2017-03-09 株式会社デンソー Input data processing system

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61107415A (en) * 1984-10-26 1986-05-26 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Interface unit
JPS61181240A (en) * 1984-12-10 1986-08-13 アメリカン　テレフオン　アンド　テレグラフ　カムパニ− Multilevel modulation signal transmitter/receiver

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61107415A (en) * 1984-10-26 1986-05-26 インタ−ナショナル　ビジネス　マシ−ンズ　コ−ポレ−ション Interface unit
JPS61181240A (en) * 1984-12-10 1986-08-13 アメリカン　テレフオン　アンド　テレグラフ　カムパニ− Multilevel modulation signal transmitter/receiver

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04362759A (en) * 1991-06-10 1992-12-15 Sharp Corp Central processing unit
US6366375B1 (en) 1997-11-10 2002-04-02 Fuji Xerox Co., Ltd. Optical-signal transmission apparatus and method, and signal processing apparatus
US6634812B2 (en) 1998-01-09 2003-10-21 Fuji Xerox Co., Ltd. Optical bus system and signal processor
US6317242B1 (en) 1998-01-09 2001-11-13 Fuji Xerox Co., Ltd. Optical bus system and signal processor
US6429838B1 (en) 1998-02-25 2002-08-06 Lg. Philips Lcd Co., Ltd. Correlation modulating apparatus
US6320590B1 (en) 1998-02-25 2001-11-20 Lg. Philips Lcd Co., Ltd. Data bus compressing apparatus
US6266722B1 (en) 1998-07-31 2001-07-24 Mitsubishi Denki Kabushiki Kaisha Multi-value logic device, bus system of multi-value logic devices connected with shared bus, and network system of information processors loaded with multi-value logic devices and connected with shared network
EP1189142A2 (en) * 2000-08-23 2002-03-20 Infineon Technologies AG Method and apparatus for exchanging data between memories and logic-modules
GB2388000B (en) * 2000-11-15 2005-03-09 Intel Corp Symbol-based signaling for an electromagnetically-coupled bus system
JP2008171393A (en) * 2006-12-14 2008-07-24 Seiko Epson Corp Signal bus, multilevel input interface, and information processor
JP2008306840A (en) * 2007-06-07 2008-12-18 Konica Minolta Holdings Inc Power management system and method of controlling power management system
WO2009084107A1 (en) * 2007-12-28 2009-07-09 Fujitsu Limited Information procesor, access method of information processor and program for making computer perform access method
JP2010061723A (en) * 2008-09-02 2010-03-18 Toppan Printing Co Ltd Semiconductor memory device
JP2013105518A (en) * 2011-11-16 2013-05-30 Samsung Electronics Co Ltd Multi-valued logic device having nonvolatile memory devices
JP2017047816A (en) * 2015-09-03 2017-03-09 株式会社デンソー Input data processing system

Also Published As

Publication number Publication date
JP2582077B2 (en) 1997-02-19

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Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees