JPS54146515A - Digital coding transmission system - Google Patents

Digital coding transmission system

Info

Publication number
JPS54146515A
JPS54146515A JP5464378A JP5464378A JPS54146515A JP S54146515 A JPS54146515 A JP S54146515A JP 5464378 A JP5464378 A JP 5464378A JP 5464378 A JP5464378 A JP 5464378A JP S54146515 A JPS54146515 A JP S54146515A
Authority
JP
Japan
Prior art keywords
circuit
information
transmission
time series
buffer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5464378A
Other languages
Japanese (ja)
Inventor
Hajime Kakehi
Masaru Iizuka
Keisuke Hoshino
Yoshiaki Kono
Yukio Kudo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP5464378A priority Critical patent/JPS54146515A/en
Publication of JPS54146515A publication Critical patent/JPS54146515A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To realize a transmission system in which a synchronization is secured between each circuit of the transmission line input/output and the signal input/ output and no distortion is given to the transmission original signal which can be delivered at the reception side by the time series exactly identical to the signal sampling time series at the transmission side.
CONSTITUTION: The information of transmission buffer 1 is sent via parallel-series conversion circuit 4 and MODEM6. Timing pulse A showing the end of information transmission shifts the next information to circuit 4 from buffer 1 and then have an interruption to set the following information to processor 2 via buffer 1. Timing pulse B under being transmitted samples input signal C through circuit 11 and then performs the A/D conversion through circuit D. The information thus transmitted is reproduced correctly at circuit groups 14∼22 shown in the figure at the reception side and through the time series synchronized with the transmissiin information.
COPYRIGHT: (C)1979,JPO&Japio
JP5464378A 1978-05-09 1978-05-09 Digital coding transmission system Pending JPS54146515A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5464378A JPS54146515A (en) 1978-05-09 1978-05-09 Digital coding transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5464378A JPS54146515A (en) 1978-05-09 1978-05-09 Digital coding transmission system

Publications (1)

Publication Number Publication Date
JPS54146515A true JPS54146515A (en) 1979-11-15

Family

ID=12976447

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5464378A Pending JPS54146515A (en) 1978-05-09 1978-05-09 Digital coding transmission system

Country Status (1)

Country Link
JP (1) JPS54146515A (en)

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