JP2010061723A - Semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device which enables high-speed information input. <P>SOLUTION: The semiconductor memory device 1 inputs a plurality of data through a data line into a plurality of memory cells specified by a signal input into an address line. A high-speed input processing part 530 defines a plurality of voltage ranges divided by a plurality of threshold voltages defined beforehand and converts a multi-value logic signal input from the outside into a binary number with multiple digits corresponding to the multi-value logic signal defined for each voltage range. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device using a multi-value logic signal as an input signal.

In a serial input and serial output file memory type semiconductor memory device represented by NAND flash memory, input data is stored in a volatile storage unit that temporarily holds data, and then stored in a nonvolatile storage unit. A batch writing process is performed (see, for example, Patent Document 1).
In recent years, the amount of data handled by such a file memory type semiconductor memory device has increased, and the capacity of the nonvolatile storage section has been increased (for example, see Non-Patent Document 1).
JP 2000-1000018 A Kuwano, “How to Use NAND Flash ROM”, CQ Publisher, Interface (March 2007 issue), p. 77-78.

By the way, as the capacity of the non-volatile storage unit in the file memory type semiconductor memory device is increased, a method of increasing the amount of data written at one time has been taken. Along with this, the write processing time becomes longer according to the amount of data written at one time.
The write processing time can be divided into an input time for inputting data into the volatile memory area of the semiconductor memory device and a transfer write time for collectively writing the input data into the nonvolatile storage unit.
For example, in the case of a file memory of 16 Gbit (gigabit), that is, 2 Gbyte (gigabyte), the memory area to be written or read simultaneously is 2 Kbyte (kilobyte (= 2048 bytes (byte))).
When writing to this memory area, if 2048 write data are input serially at the same time,

2048 × 30 (ns) = 61 (μs (microsecond))

Input time is required. The input cycle of the serial input was 30 ns (nanoseconds). On the other hand, the transfer write time requires about 200 (μs (microseconds)) since 2048 bytes (bytes) are simultaneously written at once. The write processing time in this case is about 260 (μs (microseconds)).

  Furthermore, if the amount of data to be collectively written is increased to increase the speed and the write processing is performed in a batch of 4096 bytes (bytes), the transfer write time is not changed to about 200 (μs (microseconds)). The input time for serial input is

4096 × 30 (ns) = 122 (μs (microseconds))

It becomes. In this case, the write processing time is about 320 (μs (microseconds)).
When the amount of data to be written in a lump is increased in this way, the ratio of the write data input time to the write processing time increases. For this reason, the advantage of shortening the time by batch writing is lost, which hinders speeding up.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor memory device capable of inputting information at high speed.

  In order to solve the above problem, the present invention provides a semiconductor memory device for inputting a plurality of data via a data line to a plurality of memory cells specified by a signal input to an address line. A plurality of voltage ranges divided by different threshold voltages are defined, and a multi-value logic signal input from the outside is converted into a multi-digit binary number corresponding to the multi-value logic signal determined for each voltage range. A semiconductor memory device comprising an input signal processing unit.

  According to the present invention, in the semiconductor memory device according to the invention described above, the input signal processing unit branches at least one input multi-value logic signal and binarizes the plurality of comparators having different threshold voltages. And an encoding unit for converting a plurality of binarized output signals output from the determination unit according to the logic signal into the binary digits of the plurality of digits.

  According to the present invention, in the semiconductor memory device of the above invention, the input signal processing unit is provided in an input unit of one or a plurality of the data lines.

  According to the present invention, in the semiconductor memory device of the above invention, the input signal processing unit is provided in an input unit of one or a plurality of the address lines.

  The present invention includes a plurality of memory cells, a row decoder that selects the memory cells based on an input selection signal, and a column decoder that selects the memory cells connected to a column control line based on an input selection signal. A volatile storage unit that temporarily stores information to be written to and read from the plurality of memory cells in units of transfer processing, and the plurality of memory cells are selected based on address information input from the outside. A first selection signal of the plurality of memory cells selected and a second selection signal of a storage area of the volatile storage unit corresponding to the selected memory cells are output in association with each other, and the volatile storage An address control unit for outputting the second selection signal for selecting a storage area of the unit in accordance with a control signal input from the outside, and the control signal and control information input from the outside A control processing unit that controls the writing and reading based on the information to transfer information between the volatile memory unit and the plurality of memory cells in units of transfer processing, and is determined in advance. A plurality of voltage ranges divided by a plurality of different threshold voltages are defined, and a multi-value logic signal input from the outside is converted into a multi-digit binary number corresponding to the multi-value logic signal determined for each voltage range. An input signal processing unit for converting, and the input signal processing unit is configured to write information to the volatile storage unit based on a control signal and control information input from the outside, and the address control unit A process of inputting at least one of the address information to the control information and the control information for controlling the writing to and reading from the control processing unit is performed. A body-memory devices.

According to the present invention, the semiconductor memory device simultaneously inputs the respective data to the plurality of memory cells specified by the signal input to the address line via the data line. The input signal processing unit in the semiconductor memory device defines a plurality of voltage ranges divided by a plurality of different predetermined threshold voltages, and multi-valued logic signals input from the outside are determined for each voltage range. A process of converting to a multi-digit binary number corresponding to a multi-value logic signal is performed.
Thereby, when the same amount of information is taken in, the number of input processes can be reduced, and the input process can be speeded up.

According to the present invention, in the semiconductor memory device described above, the input signal processing unit includes a determination unit and an encoding unit. The determination unit branches at least one input multi-valued logic signal and binarizes it with a plurality of comparators having different threshold voltages. The encoding unit converts the plurality of binarized output signals output from the determination unit according to the logic signal into a binary number of a plurality of digits.
Thereby, a multi-valued logic signal can be used for the input signal, and a plurality of pieces of information can be included in the signal captured by one input process. A plurality of pieces of information included in each signal can be captured at a time, the number of captures can be reduced, and input processing can be speeded up.

According to the invention, in the semiconductor memory device described above, the input signal processing unit is provided in the input unit of one or a plurality of data lines.
Thereby, the input processing from the data line can be speeded up.

According to the invention, in the semiconductor memory device described above, the input signal processing unit is provided in an input unit of one or a plurality of address lines.
Thereby, the input processing from the address line can be speeded up.

Further, according to the present invention, the input signal processing unit determines a plurality of voltage ranges divided by a plurality of different predetermined threshold voltages, and outputs the multi-valued logic signal input from the outside for each voltage range. It is converted into a multi-digit binary number corresponding to a predetermined multi-value logic signal. Further, the input signal processing unit performs information writing to the volatile storage unit, address information to the address control unit, writing to and reading from the control processing unit based on the control signal and control information input from the outside. Input processing of at least one of the control information to be controlled is performed.
As a result, the semiconductor memory device can perform input processing for data, address information, and control information indicated by multilevel logic signals, and can speed up and efficiently perform input processing for inputting information from the outside. it can.

Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a schematic block diagram showing the configuration of the semiconductor memory device according to the present embodiment.
The semiconductor memory device 1 shown in this figure is a NAND flash memory.
The semiconductor memory device 1 includes a memory area 100, a register 200, an address control unit 310, a control processing unit 410, an input / output buffer unit 510, an output buffer unit 520, and a high-speed input processing unit 530.

The memory area 100 in the semiconductor memory device 1 is a storage area in the semiconductor memory device 1. The memory area 100 includes a memory cell array 100M, a row line control unit (row decoder) 120, and a column line control unit (column decoder) 130.
Memory cell array 100M includes a plurality of memory cells arranged two-dimensionally, and each memory cell is selected based on a selection signal input via a row line and a column line, and erased with respect to the selected memory cell • Write / read processing is performed. The row line control unit 120 outputs a selection signal to the row line to which the memory cell to be selected in the memory cell array 100M is connected based on the input selection signal. The column line control unit 130 outputs a selection signal to the column line to which the memory cell to be selected in the memory cell array 100M is connected based on the input selection signal.

A configuration example in the memory cell array 100M will be described with reference to FIG.
(A) is a schematic block diagram which shows the connection relation of the memory cell arrange | positioned in multiple numbers. The plurality of memory cell shown in this figure, the memory cell _Q n1 _{to Q n32} which is a unit for storing information, a row line control signal for selecting the memory cells _Q n1 _{to Q n32} each are input WL1~WL32 When a column line CLn to the information, such as during the time and read and write in the memory cells Q _n1 to Q _n32 which are connected in series is selected is input, the memory cells Q _n1 to Q that are connected in series A reference potential to which one end of _n32 is connected is shown.
Each of the memory cells Q _{n1 to} Q _n32 is a semiconductor element that functions as a MOS transistor, and the illustrated semiconductor element is a floating gate MOS (Metal-Oxide Semiconductor) transistor having a control gate. . A control gate of each semiconductor element, a control signal for selecting the memory cells _Q n1 _{to Q n32} are connected to the row line WL1~WL32 respectively input.

One end (source) of the memory cells Q _{n1 to} Q _n32 connected in series is connected to the source line SL to which the source potential is applied, and the other end (drain) of the memory cells Q _{n1 to} Q _n32 connected in series. ) Is connected to a column line CLn. A column line controller 130 (not shown) is connected to the connected column line CLn, and when any of the memory cells Q _{n1 to} Q _n32 is selected according to address information input to the column line controller 130, Information necessary for erasing, writing, and reading is transferred to the selected memory cell via the column line CLn.
The control gates of the memory cells _Q n1 _{to Q n32,} are respectively the row lines WL1~WL32 is connected, the control signal of the memory cell to be selected is input.

(B) is a plan view showing the memory cell portion.
On the silicon substrate, memory cells Q _{n1 to} Q _n32 are formed continuously in a region surrounded by the element isolation insulating film. In each of the memory cells Q _{n1 to} Q _n32 , a floating gate (FG) is formed on the substrate via an insulating film to form a charge storage layer. A control gate is formed thereon via an insulating film, and the control gate is connected to the respective row lines WL1 to WL32.

The register 200 in the semiconductor memory device 1 is a volatile storage area that temporarily stores information in the write / read processing for the memory area 100.
With reference to the drawings, operations related to the memory area 100 and the register 200 in the semiconductor memory device 1 that performs serial input / output will be described.
FIG. 3 is a diagram illustrating an erasing operation of the semiconductor memory device.
In this figure, a memory area 100 in the semiconductor memory device 1, a block processing area 110 provided in the memory area 100, and a register 200 are shown.
The same reference numerals are given to the same components as those described above, and the block processing areas 110 having different configurations will be described.
The memory area 100 is divided into a plurality of blocks, one of which is shown as a block processing area 110. The block processing area 110 is an area where an erase operation, a write operation, and a read operation are performed for each block. The block processing area 110 shown in this figure has a capacity of 2048 (2 kbytes (kilobytes) × 8 bits (bits)) columns × 32 rows. For example, the storage area of 524,288 cells can be processed simultaneously. Become. The register 200 is an area for temporarily storing information to be input / output when an erase operation, a write operation, and a read operation are performed on the block processing area 110. In the erasing operation shown in this figure, the information stored in the block processing area is erased by a single erasing process on the block processing area 110. In the erase operation, processing is performed without the register 200 being interposed.

FIG. 4 is a diagram showing a write operation of the semiconductor memory device.
The same reference numerals are given to the same components as those described above, and the pages 111 having different configurations will be described.
The block processing area 110 in the memory area 100 is divided into a plurality of pages, one of which is shown as a page 111. The page 111 is an area where a write operation and a read operation are performed in units of pages. The capacity of the page 111 shown in this figure shows an example of 2048 bytes (bytes (= 2 kbytes (kilobytes))). One page capacity of 2 kBytes (kilobytes) is 16,384 cells (2048 × 8 bits (bits)). That one page storage area is written simultaneously. In addition, one page of data is input to the register 200 by serial input. Then, a write process in units of pages is performed from the register 200 to the page 111.

FIG. 5 is a diagram illustrating a read operation of the semiconductor memory device.
The same reference numerals are given to the same components as those described above, and a read operation via the register 200 will be described.
A page-by-page read process is performed from the page 111 to the register 200. Then, one page of data is output from the register 200 as serial output.

  Further, the address control unit 310 in the semiconductor memory device 1 generates a selection signal for the memory cell selected based on the input address information and the control signal, and the row line control unit 120 and the column in the memory region 100 are generated. Input to the line control unit 130. In addition, the address control unit 310 outputs address information of the register 200 necessary for information transfer to the register 200. The row line control unit 120, the column line control unit 130, and the register 200 can operate in cooperation with each other by the selection signal output from the address control unit 310, and transfer processing inside the semiconductor memory device 1 can be performed.

  The control processing unit 410 in the semiconductor memory device 1 generates a timing signal in each processing in the semiconductor memory device 1 based on the input control signal and control information (command), and outputs the timing signal to the register 200 and the address control unit 310. . The control processing unit 410 includes a storage unit that stores input control information (command) and a determination processing unit that determines the stored information. In addition, the control processing unit 410 outputs a signal indicating a processing state based on the generated timing signal.

The input / output signals of the semiconductor memory device 1 input / output via the input / output buffer unit 510, the output buffer unit 520, and the high-speed input processing unit 530 will be described with reference to the drawings.
FIG. 6 is a configuration example showing connection of the semiconductor memory device 1 to the outside.
In this figure, a semiconductor memory device 1 and a system bus 2 (System Bus) 2 to which the semiconductor memory device 1 is connected are shown. There are a plurality of signals connected to the system bus 2, and there are a data bus signal for inputting / outputting information and a control signal for controlling input / output of information.
The data bus shown in this figure shows an example in which input / output can be performed in parallel with 8 bits (bits). A command input method is used for the interface specification with the system bus 2. By this command input method, I / O1 terminal to I / O8 terminal (hereinafter referred to as I / O1 terminal to I / O8 terminal) that commonly use input / output of all information of address input, data input, and data output are summarized. (Referred to as “I / O terminal”). By using these terminals for serial input and serial output, the number of pins can be greatly reduced, and the pin arrangement compatibility can be maintained without depending on the memory capacity.

In addition, the semiconductor memory device 1 has a / CE terminal, a / RE terminal, a / WE terminal, an R / BY terminal, an ALE terminal, a control signal terminal to which a signal for controlling the input / output timing of the I / O terminal is input / output. A CLE terminal and a / WP terminal are provided.
Each control signal terminal (/ CE terminal, / RE terminal, / WE terminal, R / BY terminal, ALE terminal, CLE terminal, and / WP terminal) has a / CE signal, / RE signal, / WE as its control signal. A signal, an R / BY signal, an ALE signal, a CLE signal, and a / WP signal are input. The R / BY terminal outputs an R / BY signal as a status display signal.

The function of each signal will be described.
The / CE signal indicates a chip enable signal and is an input signal used as a selection signal for the semiconductor memory device. The / RE signal indicates a read enable signal and is an input signal used when reading data through the I / O terminal. The / WE signal indicates a write enable signal and is an input signal used when writing data via the I / O terminal. The ALE signal indicates an address latch enable signal, and is an input signal used when address information or input data is taken into an address register inside the semiconductor memory device. When “H (high)” is input to this signal, the address information is taken in by the rise of the / WE signal, and when “L (low)” is input to this signal, the / WE signal rises. As a result, the input data is captured. The CLE signal indicates a command latch enable signal and is an input signal used when an operation command is taken into a command register inside the semiconductor memory device. The / WP signal indicates a write protect signal, and is a signal for preventing unexpected writing or erasing when the input signal is indeterminate. The R / BY signal indicates a ready / busy signal and is a signal for displaying an operation state inside the semiconductor memory device.

In the semiconductor memory device 1, write / read information and control signals are input / output via the input / output buffer unit 510, the output buffer unit 520, and the high-speed input processing unit 530.
The input / output buffer unit 510 in the semiconductor memory device 1 is an input / output processing unit that performs control signal input processing and status display signal output processing. The output buffer unit 520 is an output processing unit that outputs read data to the I / O terminal. The high-speed input processing unit 530 is an input processing unit that performs an input process of address information, write data, and control information (command) input from the I / O terminal.

Details of the high-speed input processing unit 530 will be described with reference to the drawings.
FIG. 7 is a diagram illustrating an input / output relationship in the high-speed input processing unit 530.
The table shown in this figure shows the standard voltage of the signal input to the high-speed input processing unit 530, the result of binarizing information indicated by the voltage of the input signal, and the information in two consecutive memory cells. Indicates the association of data to be written.
The items in each column of this table are “input voltage (four values)” of the input signal, “binary logic” indicating information included in the input signal, “DIN * (Odd)” and “DIN * ( Even) ". The items in each row indicate 0.0 V (volt), 0.6 V (volt), 1.2 V (volt), and 1.8 V (volt) as standard voltages of the input signal DIN.
This table shows the logical value of each column converted according to the voltage of the input signal. For example, if the input voltage is 0.6V (volt), the input voltage is converted, and “1” and “0” are output to the output signals DIN * (Odd) and DIN * (Even), respectively. The

The configuration of the high-speed input processing unit 530 in the semiconductor memory device 1 will be described with reference to the drawings.
FIG. 8 is a block diagram illustrating a configuration of the high-speed input processing unit 530.
The high-speed input processing unit 530 in the semiconductor memory device 1 includes a comparison processing unit 10 and an encoder unit 20.
The comparison processing unit 10 in the high-speed input processing unit 530 makes a determination by comparing the voltages of the signals DIN1 to DINn input from the I / O terminals with a predetermined threshold value, and the determination result is output as the output signals din11 to din83. A plurality of voltage comparison circuits 11, 12,.

FIG. 9 is a block diagram illustrating a configuration of one voltage comparison circuit 11 in the comparison processing unit 10.
The voltage comparison circuit 11 shown in this figure includes an input terminal TDIN1 to which an input signal DIN1 is input, and comparators CMP11, 12 and 13.
A non-inverting input of each of the comparators CMP11, 12 and 13 is connected to the input terminal TDIN1, and an inverting input of each of the comparators CMP11, 12 and 13 is connected to a reference potential Vref1, Vref2 and Vref3, respectively. The outputs of the comparators CMP11, 12 and 13 are connected to output terminals Tdin11, 12 and 13. The reference potentials Vref1, Vref2, and Vref3 in this figure are 0.3 V (volt), 0.9 V (volt), and 1.5 V (volt), respectively.
The voltage comparison circuit 11 determines the voltage of a signal input to one input terminal TDIN1 with a threshold voltage determined by the reference potentials Vref1, Vref2, and Vref3, and the voltage of the input signal is set stepwise. It is determined which range of the threshold value corresponds to. The voltage comparison circuit 11 shown in this figure can determine in which voltage range the input signal is divided into four voltage ranges.

FIG. 10 is a block diagram showing a configuration of one encoder circuit 21 in the encoder unit 20.
The encoder circuit 21 includes inverters IV1, IV2, and IV3, and NOR (nor) 1 and NOR2.
The input terminal Tdin2 is connected to the input terminal of the inverter IV1. The input terminal Tdin1 is connected to one input terminal of NOR1, and the output terminal of the inverter IV1 is connected to the other input terminal of NOR1. The input terminal Tdin3 is connected to one input terminal of NOR2, the other input terminal of NOR2 is connected to the output terminal of NOR1, and is connected to the output terminal TDIN * (Odd) via the inverter IV3. The output terminal of the inverter IV1 is connected to the output terminal TDIN * (Even) via the inverter IV2.

FIG. 11 is a diagram illustrating operations of the voltage determination circuit 11 and the encoder circuit 21 in the high-speed input processing unit 530.
The table shown in the figure shows the relationship between the standard voltage of the signal input to the high-speed input processing unit 530, the output signal of the voltage determination circuit 11 at each input level, and the output signal of the encoder circuit 21. The items in each column of this table indicate 0.0 V (volt), 0.6 V (volt), 1.2 V (volt), and 1.8 V (volt) as standard voltages of the input signal DIN. The items in each row of this table indicate intermediate signals din1, 2 and 3, and output signals DIN * (Odd) and DIN * (Even). In the array indicated by each column and each row, the logical state of each signal corresponding to the voltage of the input signal DIN is indicated.

The timing of input / output signals of the semiconductor memory device will be described with reference to the drawings.
FIG. 12 is a timing chart showing address information input processing of the semiconductor memory device.
In the timing chart shown in this figure, the timing at which each signal is transitioned when an operation in which address information is input in subsequent cycles T _{A1 to} T _A3 is performed in accordance with a command input in cycle T _CMD1 is shown. Has been. The transition of signals in each cycle will be described according to this timing chart.

Prior to the address information input process, “L (low)” is set for the CLE terminal, “L (low)” is set for the / CE terminal, “H (high)” is set for the / WE terminal, and “L (low)” is set for the ALE terminal. L (low) "is input. Thereby, the I / O terminal becomes high impedance (time t _a0 ).

In cycle T _CMD1 , “H (high)” is input to the CLE terminal, “L (low)” is input to the / WE terminal, and a signal indicating command (CMD) information is input to the system bus 2 at the I / O terminal. Set through. When “H (high)” is input to the / WE terminal, information indicated by the signal set in the I / O terminal at the rising timing of the / WE signal is recorded in the storage unit in the internal command determination unit. Is done. Processing for determining command (CMD) information stored in the storage unit is performed, and it is determined that the subsequent cycle is a cycle in which address information is input. Again, “L (low)” is input to the / CE terminal, and the I / O terminal becomes high impedance (time t _a1 ).

In cycle T _A1 , “H (high)” is input to the ALE terminal, “L (low)” is input to the / WE terminal, and a signal indicating address information (Add) is input to the I / O terminal. Is set via When “H (high)” is input to the / WE terminal, a signal set to the I / O terminal at the rising timing of the / WE signal is taken into the internal address determination unit, and a part of the address information Set as Again, “L (low)” is input to the / CE terminal, and the I / O terminal becomes high impedance (time t _a2 ).
In the cycle T _A2 and the cycle T _A3 , the same operation cycle as the cycle T _A1 is repeatedly performed, and the address information is fetched in a divided manner.
The address information shown in this figure is input in three cycles, but the input information can be input as 6-byte (byte) information.

FIG. 13 is a timing chart showing data input processing of the semiconductor memory device.
This timing chart shows the timing of transition of each signal when an operation in which data information is input in subsequent cycles T _{D1 to} T _D3 is performed according to a command input in cycle T _CMD2 . The transition of signals in each cycle will be described according to this timing chart.

Prior to the address information input process, “L (low)” is set for the CLE terminal, “L (low)” is set for the / CE terminal, “H (high)” is set for the / WE terminal, and “L (low)” is set for the ALE terminal. L (low) "is input. Thereby, the I / O terminal becomes high impedance (time _td0 ).

In cycle _TCMD2 , “H (high)” is input to the CLE terminal, “L (low)” is input to the / WE terminal, and a signal indicating command (CMD) information is input to the system bus 2 at the I / O terminal. Set through. When “H (high)” is input to the / WE terminal, the signal set in the I / O terminal at the rising timing of the / WE signal is recorded in the storage unit in the internal command determination unit. The command (CMD) information stored in the storage unit is subjected to determination processing as command information, and it is determined that the subsequent cycle is a cycle in which data information is input. Again, “L (low)” is input to the / CE terminal, and the I / O terminal becomes high impedance (time t _d1 ).

In cycle _TD1 , “H (high)” is input to the ALE terminal, “L (low)” is input to the / WE terminal, and a signal indicating input data (Data) is input to the I / O terminal. Is set via When “H (high)” is input to the / WE terminal, the signal set to the I / O terminal at the rising timing of the / WE signal is recorded in the internal register. Again, “L (low)” is input to the / CE terminal, and the I / O terminal becomes high impedance (time t _d2 ).
In the cycle T _D2 and the cycle T _D3 , the same operation cycle as the cycle T _D1 is repeatedly performed, and the data information is repeatedly stored in the register.
The data input shown in this figure is performed in three cycles, but the input information can be input as 6-byte (byte) information.

FIG. 14 is a timing chart showing data input processing of the semiconductor memory device.
This timing chart shows the transition timing of each signal in the operation of recording 10 data in 5 cycles in the storage area indicated by consecutive addresses A0 to A9. A signal transition in each cycle will be described.
For details of the address information (Address (ADD)), the input signal DIN, and the output signals DIN * (Odd) and DIN * (Even) shown in this timing chart, refer to the above description and change in each cycle. Will be described.

In the cycle T ₀ , “A0” is set as address information, and 1.2 V (volts) is input to the input signal DIN, so that “H (high)” is output to the output signal DIN * (Odd). "Is output to DIN * (Even) as" L (low) ". In the cycle T ₁ , “A2” is set as address information, and 0.6 V (volt) is input to the input signal DIN, so that “L (low)” is output to the output signal DIN * (Odd). ”Is output to DIN * (Even) as“ H (high) ”. In the cycle T ₂ , “A4” is set as the address information, and 0.0 V (volt) is input to the input signal DIN, so that “L (low)” is output to the output signal DIN * (Odd). "Is output to DIN * (Even) as" L (low) ". In cycle T ₃ , “A6” is set as the address information, and 1.8 V (volts) is input to the input signal DIN, so that “H (high) is output to the output signal DIN * (Odd)”. ”Is output to DIN * (Even) as“ H (high) ”. In cycle T ₄ , “A8” is set as address information, and 0.6 V (volts) is input again to the input signal DIN, so that “L (low) is output to the output signal DIN * (Odd). ) ”Is output as“ H (high) ”in DIN * (Even).

  In this way, data can be written into each cell indicated by DIN * (Odd) and DIN * (Even) in one cycle. An address serving as an index for referring to the DIN * (Odd) and DIN * (Even) is indicated by Ai (i is an integer). Two consecutive cells can be written simultaneously. That is, the information indicated by the output signal DIN * (Odd) at the address Ai (i = 2 × n), and the information indicated by the output signal DIN * (Even) at the address Ai (i = 2 × n + 1). Are simultaneously written in the same write cycle.

FIG. 15 shows the operation shown in FIG. 14 as a table.
Addresses A0 and A1, addresses A2 and A3, addresses A4 and A5, addresses A6 and A7, and addresses A8 and A9 are written to two addresses in the same cycle. . That is, to write 10 pieces of data, it can be performed by taking in 5 times, and is processed in 5 write cycles.

FIG. 16 is a timing chart showing data input processing of the semiconductor memory device according to the conventional embodiment.
In an input method that does not use a multi-valued logic signal as an input signal, data captured by one input process is written to a predetermined address each time.
FIG. 17 is a diagram showing the operation shown in FIG. 16 as a table.
From the addresses A0 to A9, the data fetched by one input process is written in order in the same cycle.
That is, in order to write 10 pieces of data, 10 captures are required and processing is performed in 10 write cycles. In the above-described write processing in the present embodiment, the input signal is defined as a four-value logic signal, so that the input processing can be performed with half the number of cycles of the conventional method.

The present invention is not limited to the above embodiments, and can be modified without departing from the spirit of the present invention. Although a NAND flash memory is shown as an example of the semiconductor memory device in the present embodiment, a semiconductor memory device having another configuration may be used.
Further, although the terminal for performing high-speed input processing has been described as an I / O terminal that uses an address terminal and a data terminal in common, the present invention is applied to a semiconductor memory device having a configuration in which the address terminal and the data terminal are separated. Also good.
Further, although the number of simultaneously input signals is processed by the eight I / O terminals, other signal numbers may be used in accordance with the required number of signals.

Further, when the voltage of the input signal is determined in a further subdivided voltage range, it is possible to use a voltage comparison circuit 31 instead of the voltage determination circuit 11 as shown in FIG. . The voltage comparison circuit 11b includes an input terminal TDIN1 to which an input signal DIN1 is input, and comparators CMP31, 32, 33, 34, 35, 36, and 37.
The non-inverting input of each comparator CMP31, 32, 33, 34, 35, 36 and 37 is connected to the input terminal TDIN1, and the inverting input of each comparator CMP31, 32, 33, 34, 35, 36 and 37 is a reference. Connected to the potentials Vref1, Vref2, Vref3, Vref4, Vref5, Vref6 and Vref7, respectively. The outputs of the comparators CMP31, 32, 33, 34, 35, 36, and 37 are connected to output terminals Tdin11, 12, 13, 14, 15, 16, and 17, respectively.
The reference potentials Vref1, Vref2, Vref3, Vref4, Vref5, Vref6, and Vref7 in this figure are 0.8V (volt), 0.9V (volt), 1.0V (volt), 1.1V (volt), 1 .2V (volt), 1.3V (volt), 1.4V (volt). That is, the voltage comparison circuit 31 can determine whether a signal in a voltage range obtained by dividing the input signal into eight is input. The encoder connected to the voltage comparison circuit 31 can also apply 3 bits (bits) of information that can be input simultaneously by adapting the 8-input 3-output type priority encoder circuit.

1 is a schematic block diagram illustrating a configuration of a semiconductor memory device according to an embodiment of the present invention. 2 is a schematic block diagram showing a configuration of a memory cell in the semiconductor memory device according to the present embodiment. FIG. FIG. 10 is a diagram illustrating an erasing operation of the semiconductor memory device according to the present embodiment. FIG. 10 is a diagram showing a write operation of the semiconductor memory device according to the present embodiment. FIG. 10 is a diagram showing a read operation of the semiconductor memory device according to the present embodiment. 2 is a configuration example showing connection of the semiconductor memory device according to the present embodiment to the outside. It is a figure which shows the data input process of the semiconductor memory device by the conventional embodiment. It is a block diagram (the 1) which shows the structure of the high-speed input circuit by this embodiment. It is a block diagram (the 2) which shows the structure of the high-speed input circuit by this embodiment. It is a block diagram (the 3) which shows the structure of the high-speed input circuit by this embodiment. It is a figure which shows operation | movement of the high-speed input circuit by this embodiment. 5 is a timing chart showing address information input processing of the semiconductor memory device according to the present embodiment. 4 is a timing chart showing a data input process of the semiconductor memory device according to the present embodiment. 4 is a timing chart showing continuous data input processing of the semiconductor memory device according to the present embodiment. It is a figure which shows the data input process of the semiconductor memory device by this embodiment. 6 is a timing chart showing continuous data input processing of a semiconductor memory device according to a conventional embodiment. It is a figure which shows the data input process of the semiconductor memory device by the conventional embodiment. It is a block diagram (the 2) which shows the structure of the high-speed input circuit by this embodiment.

Explanation of symbols

1 Semiconductor memory device 1
100 memory area, 100M memory cell array 120 row line control unit, 130 column line control unit 200 register 310 address control unit 410 control processing unit 510 input / output buffer unit, 520 output buffer unit, 530 high-speed input processing unit

Claims (5)

A semiconductor memory device for inputting a plurality of data via a data line to a plurality of memory cells specified by a signal input to an address line,
A plurality of voltage ranges divided by a plurality of predetermined different threshold voltages are defined, and a multi-valued logic signal input from the outside is a multi-digit 2 corresponding to the multi-valued logic signal determined for each voltage range. A semiconductor memory device comprising an input signal processing unit for converting to a decimal number. The input signal processor is
A decision unit for branching at least one input multi-valued logic signal and binarizing with a plurality of comparators having different threshold voltages; and binarization output by the decision unit according to the logic signal An encoding unit for converting a plurality of output signals into the binary digits of the plurality of digits;
The semiconductor memory device according to claim 1, further comprising: The input signal processor is
The semiconductor memory device according to claim 1, wherein the semiconductor memory device is provided at an input portion of the one or more data lines. The input signal processor is
4. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is provided in an input portion of one or a plurality of the address lines. 5. A plurality of memory cells; a row decoder that selects the memory cells based on an input selection signal; a column decoder that selects the memory cells connected to a column control line based on an input selection signal; A plurality of memory cells that are selected based on address information input from the outside, and a volatile storage unit that temporarily stores information to be written to and read from the memory cells in units of transfer processing A first selection signal of the memory cell and a second selection signal of the storage area of the volatile storage section corresponding to the selected plurality of memory cells are output in association with each other, and the storage area of the volatile storage section An address control unit that outputs the second selection signal according to a control signal input from the outside based on the control signal and control information input from the outside And controls the serial writing and reading, a semiconductor memory device and a control processing unit for transferring the transfer process unit information between said volatile type memory unit said plurality of memory cells,
A plurality of voltage ranges divided by a plurality of predetermined different threshold voltages are defined, and a multi-valued logic signal input from the outside is a multi-digit 2 corresponding to the multi-valued logic signal determined for each voltage range. An input signal processing unit for converting to a hexadecimal number;
With
The input signal processor is
Based on the control signal and control information input from the outside, the information to be written to the volatile storage unit, the address information to the address control unit, and the writing and reading to the control processing unit are controlled. An input process of at least one of the control information is performed. A semiconductor memory device.

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