JPH03177922A - Wallence tree circuit - Google Patents

Abstract

PURPOSE:To decrease the number of component elements and to reduce the scale of a wallence tree circuit by handling the input values of a full adder and a half adder in terms of a negative logic. CONSTITUTION:A full adder 700 consists of the AND circuits 710 - 730, a NOR circuit 740, and the exclusive OR circuits 750 and 760 and receives the supply of the inverted inputs A - C. The circuit 740 outputs the carry output C which is supplied to the next stage, and the circuit 760 outputs the addition output S. The inverted inputs A and B are supplied to a NOR circuit 810 and an AND circuit 820 via a half adder 800. The output of the circuit 810 is used as the output C and at the same time this output C and the AND output are supplied to a NOR circuit 830 to undergo the NOR processing and to be used as the output S. As a result, the number of component elements can be decreased for both adders 700 and 800. Then the scale of a wallence tree circuit is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an adder circuit, particularly a Wallace tree circuit, which is suitable for application to a parallel multiplier that is processed using Booth's algorithm.

"Conventional Technology J Parallel multipliers that multiply digital signals have a larger circuit scale than serial-parallel multipliers, but they are now widely used because their calculation speed is fast and they can be integrated into LSI." It has become to.

Among these parallel multipliers, there is one that uses a modified Boot 1) algorithm as a means for particularly high-speed multiplication processing. This is the multiplier Y and the multiplicand
The purpose is to obtain the total product by adding the partial products of .

The Booth encoder obtains the signals (sign selection (g code, double selection signal, single selection signal) required for generating partial products) from the multiplier Y.

FIG. 7 is a diagram for explaining multiplication processing by partial products using the 2-bit Booth algorithm. The meaning of 2 bits here is the multiplier Y (e.g. 8-bit configuration yO
~y7) is separated by 2 bits from its LSBIII,
This refers to pits when processing is performed on two bits (actually, three bits, since 1 bits are used in overlap).

When performing 8x8 bit multiplication from each 2 bit of multiplier Y and multiplicand X (also 8 bits, xO to x7), four partial products 1 to 4 are generated as shown in Figure 7 be done. Then, the respective partial products 1 to 4 are added. During this addition process, complement conversion bits Sao to Sd6 are added to the LSB of each partial product 1 to 4. The complement conversion bit is for converting a negative partial product into a two's complement.

Wallace (1/a l 1ence) tree is one of the addition means that performs the addition process of partial products at high speed.
) circuit is known.

FIG. 8 shows an example of a parallel multiplier that performs multiplication according to Booth's algorithm and also performs partial product addition at high speed using a Wallace tree circuit.

The figure shows an 8 x 8 bit multiplier HM, in which four partial product circuits 1 are used to perform partial product processing between the multiplier Y and the multiplicand X.
0 to 40 are provided.

The partial product circuits 10 to 40 shift or invert the multiplicand X based on the Booth encoders IOA to 40A to which the multiplier Y is supplied in 2-bit increments and the selection signals output from these encoders IOA to 40A. thick inverters IOB to 40B.

Partial product 4 (Fig. 7) is output from the thick inverter IOB, and similarly, the thick inverters 20B to 40B
Partial products 3 to 1 (Fig. 7) are output.

The adder circuit 50 includes a Wallace tree circuit 50A to which partial products 1 to 4 are supplied, and a CLA adder (CLA is an abbreviation for Carry Look Ahead) 50B to which the output thereof is supplied. Therefore, the multiplication output Po=P14 is obtained.

FIG. 9 shows an example of a Wallace tree circuit used in such a parallel multiplier.

FIG. 9 shows a part of the Wallace tree circuit focusing on a certain digit, in which a full adder Who and a half adder N80 are prepared as the first stage adder to which multiple inputs are supplied.

In this example, the addition process of five inputs is illustrated, so the five inputs are
two inputs are provided to the full adder 70 and the half adder W80,
Each of them outputs a carry output C and an addition output S for one problem. Then, this addition output and the carry output C from the lower order are input to the second stage full adder M90. A pair of carry output C and addition output S are obtained from the full adder 90.

FIG. 10 is a specific example of full addition M70.90.

In the figure, 3
AND circuits 71 to 73, NOR circuit 74, two exclusive OR circuits 75 and 76, and inverter 7.
It consists of 7.

Figure 11 is half addition! This is an example of 80. This half addition N8
0 is composed of a NAND circuit 81, two NOR circuits 82 and 83, an AND circuit 84, and an inverter 85.

"Problem to be Solved by the Invention" As will be described later, as the number of digits to be added increases, the number of full adders and half-width 01s used in the Wallace tree circuit increases accordingly.

Therefore, in order to reduce the circuit size of the Wallace tree circuit, thereby reducing the circuit area and cost, the number of circuit elements in the full adder 70°90 and half adder 80, which are its basic configuration, should be reduced as much as possible. There is a need.

However, the full adder 70.90 and the half adder 80 are
In the case of the configuration as shown in FIG. 1 and FIG. 11, the number of constituent elements is relatively large, so when the entire Wallace tree circuit is viewed, the number of elements is considerable.

Therefore, the present invention proposes a Wallace tree circuit which is designed to reduce the circuit scale by reducing the number of constituent elements as much as possible.

"Means for Solving the Problems" In order to solve the above-mentioned problems, the present invention provides a Wallace tree circuit in which full adders and half adders are arranged in a tree shape to perform multi-input addition processing. The present invention is characterized in that the input values of the full adder and half adder are handled using negative logic.

"Operation" Both the full adder N700 and the half-angle H unit 800 received at the first stage have a negative logic configuration.

Therefore, the full adder N700 can be configured, for example, as shown in FIG. 2, and the half-tone W, 800 can be configured as shown in FIG.

Therefore, in the full adder 700, 34 transistors are conventionally used, but in this invention, 34 transistors are used.
It can be configured with two transistors.

Further, the half adder 800 can be configured with 10 transistors in the present invention, whereas conventionally there are 16 transistors.

When multiplier Y1 and multiplicand X are both 8 bits, partial!
When fIl~ portion 14 is output as a negative logic,
Wallace's tree circuit 50A, as shown in Figure 6, performs negative logic full addition! 3 pieces of 700, 20 pieces of negative logic half adder 800
Therefore, the reduction effect of transistors is (34-32)X3+ (16-10)X20=126
(pieces) becomes.

Embodiment Next, an example of a main part of the Wallace tree circuit 60 applicable to the parallel multiplier according to the present invention will be described in detail with reference to FIG. 1 and subsequent figures.

Also in this invention, as shown in FIG. 1, as an adder for performing addition processing of a certain digit, a full adder N700 and a half adder 800 are provided at the first stage, and a full adder W90 is provided at the second stage.

A full adder M700 and a half adder 8 are placed in the first stage.
Each input value of 00 is treated as a negative logic.

Therefore, a full adder having the configuration shown in FIG. 10 is used as the second stage full adder N90, whereas a full adder M700 having a negative logic configuration is configured as shown in FIG. 2.

As shown in FIG. 2, this full adder 700 includes AND circuits 710 to ? 3
0, a NOR circuit 740 that performs the negative OR of these outputs, an exclusive OR circuit 750 that performs the exclusive OR of the inverted inputs A and B, and an exclusive OR of the negative of this logic output and the inverted input C. Exclusive Noah circuit 760 that takes
It consists of

Then, the NOR circuit 740 outputs a carry output C to be supplied to the next stage, and the exclusive NOR circuit 760 outputs an addition output S. Therefore, this full adder 7
The truth table for 00 is shown in FIG.

FIG. 3 is a specific example of a half adder 800 having a negative logic configuration.

In the figure, inverting inputs A and B are supplied to a NOR circuit 810 and an AND circuit 820, and the output of the NOR circuit 810 is used as a carry output C, and this carry output and AND output are roughly supplied to a NOR circuit 830. is subjected to NOR processing, and this is used as the addition output S.

A truth table for half adder 800 is shown in FIG.

With this configuration, as is clear from the comparison with FIGS. 10 and 11, the total addition 170 of the negative logic configuration
0 is omniscient with a positive logic configuration! M? Compared to 0, the number of inverters can be reduced by one, and when comparing the number of elements, the number of transistors is 34 for the former and 32 for the latter.

Further, between the half adder 800 having a negative logic configuration and the half adder 80 having a positive logic configuration, the former has one fewer NAND circuit and one inverter. Therefore, the number of transistors is 16 for the former and 10 for the latter.

Now, when the parallel multiplier is configured as shown in FIG. 8, and partial products 1 to 4 are all negative logic outputs, the Wallace tree circuit 50A that adds these partial product outputs is shown in FIG. , B, and C.

As is clear from A and C in the same figure, a total of three full adders 700 with a negative logic configuration are used, and a half adder 8 with a negative logic configuration is used.
A total of 20 00s are used as shown in A to C in the figure. Others are conventional full adder 70.90 and half adder M8
0 is used.

Therefore, when using the configuration of this invention, the effect of reducing the number of transistors is (34-32)X3+ (16-10)x20=12
6 (pieces), which can reduce the number of elements by 126 compared to the conventional one, so the circuit scale can be reduced by that much.

Note that the number of multiplication bits is not limited to 8×8 bits in this example;
It can be implemented with any bit. The effect of reducing the number of elements becomes more significant as the number of bits increases.

"Effects of the Invention" As explained above, in the present invention, the input values to the first stage full adder and half adder are handled by negative logic.

According to this, since the number of constituent elements of the full adder and the half adder can be reduced, a reduction effect can be obtained for the entire circuit.

Therefore, there is a practical benefit in that the circuit scale can be reduced.

[Brief explanation of drawings]

Figure 1 is a connection diagram showing an example of a Wallace tree circuit, Figure 2 is a connection diagram of a full adder used in this, Figure 3 is a connection diagram of a half adder, and Figure 4 is a connection diagram of a full adder. Figure 5 is a diagram showing the truth table of the half adder, Figure 6 is the overall configuration diagram of the Wallace tree circuit, Figure 7 is an illustration of parallel multiplication processing, and Figure 8 is the diagram showing the truth table of the half adder. Parallel multiplication processing system diagram: Figure 9 is a connection diagram of the Wallace tree circuit used in this process, Figure 10 is a connection diagram of a conventional full adder used in this process, and Figure 11 is a connection diagram of a conventional full adder used in this process. It is a connection diagram. 10~40 10A~4OA 10B~40B 0 0A 0B 70.90 700 80, 800 ・Partial product circuit・Booth encoder・Shifter・Inverter・Adder circuit・Wallace tree circuit・CLA adder・Full adder・Half adder vessel

Claims (1)

[Claims] (1) In a Wallace tree circuit that performs multi-input addition processing by arranging full adders and half adders in a tree shape, the input values of the full adders and half adders are handled using negative logic. Wallace's tree circuit featuring .