JPS57114957A - Interface system between central processing device and main storage device - Google Patents

Interface system between central processing device and main storage device

Info

Publication number
JPS57114957A
JPS57114957A JP1681A JP1681A JPS57114957A JP S57114957 A JPS57114957 A JP S57114957A JP 1681 A JP1681 A JP 1681A JP 1681 A JP1681 A JP 1681A JP S57114957 A JPS57114957 A JP S57114957A
Authority
JP
Japan
Prior art keywords
register
main storage
readout
storage device
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1681A
Other languages
Japanese (ja)
Inventor
Kiyoshi Senba
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP1681A priority Critical patent/JPS57114957A/en
Publication of JPS57114957A publication Critical patent/JPS57114957A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To achieve readout priority processing at all times and to increase the processing ability of a central processor, by providing interfaces to the central processor and a main storage device separately for readout and write-in. CONSTITUTION:Interfaces 102a and 102b or 202a and 202b are provided corresponding to a register 1-2 or 2-2 where a readout instruction at central processing device 1' or 2' is set, and a register 1-3 or 2-3 where a write-in instruction is set, and a main storage device 3' is provided with input registers 3'-1a and 3'-1b or 3'-2a and 3'-2b corresponding to the interfaces, the output of the input registers is given to a switching circuit 3'-3, one of them is selected and given to a transfer register 3-4. When write-in is waited for the input register 3'-1b, the readout instruction is set to the register 1-2, the instruction is transferred to the register 3'-1a via the interface 102a, and the switching of the readout priority is made at the switching circuit 3'-3.
JP1681A 1981-01-05 1981-01-05 Interface system between central processing device and main storage device Pending JPS57114957A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1681A JPS57114957A (en) 1981-01-05 1981-01-05 Interface system between central processing device and main storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1681A JPS57114957A (en) 1981-01-05 1981-01-05 Interface system between central processing device and main storage device

Publications (1)

Publication Number Publication Date
JPS57114957A true JPS57114957A (en) 1982-07-17

Family

ID=11462626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1681A Pending JPS57114957A (en) 1981-01-05 1981-01-05 Interface system between central processing device and main storage device

Country Status (1)

Country Link
JP (1) JPS57114957A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988009017A1 (en) * 1987-05-06 1988-11-17 Fujitsu Ten Limited Method and apparatus for data transfer
JPS63311466A (en) * 1987-06-13 1988-12-20 Fujitsu Ten Ltd Write or read system
JP2007147499A (en) * 2005-11-29 2007-06-14 Hoshizaki Electric Co Ltd Method of confirming silver component in electrolytic generated water, and dispenser for electrolytic generated water provided therewith

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1988009017A1 (en) * 1987-05-06 1988-11-17 Fujitsu Ten Limited Method and apparatus for data transfer
US5170469A (en) * 1987-05-06 1992-12-08 Fujitsu Ten Limited Data transfer apparatus and data transfer system
JPS63311466A (en) * 1987-06-13 1988-12-20 Fujitsu Ten Ltd Write or read system
JP2007147499A (en) * 2005-11-29 2007-06-14 Hoshizaki Electric Co Ltd Method of confirming silver component in electrolytic generated water, and dispenser for electrolytic generated water provided therewith

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