FR2421441A1 - Information shunting system for digital processor - uses two registers and code lines between individual storage cells - Google Patents

Information shunting system for digital processor - uses two registers and code lines between individual storage cells

Info

Publication number
FR2421441A1
FR2421441A1 FR7809664A FR7809664A FR2421441A1 FR 2421441 A1 FR2421441 A1 FR 2421441A1 FR 7809664 A FR7809664 A FR 7809664A FR 7809664 A FR7809664 A FR 7809664A FR 2421441 A1 FR2421441 A1 FR 2421441A1
Authority
FR
France
Prior art keywords
storage cells
registers
information
code lines
digital processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7809664A
Other languages
French (fr)
Other versions
FR2421441B1 (en
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GUSEV VALERY
Original Assignee
GUSEV VALERY
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by GUSEV VALERY filed Critical GUSEV VALERY
Priority to FR7809664A priority Critical patent/FR2421441A1/en
Publication of FR2421441A1 publication Critical patent/FR2421441A1/en
Application granted granted Critical
Publication of FR2421441B1 publication Critical patent/FR2421441B1/fr
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/015—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising having at least two separately controlled shifting levels, e.g. using shifting matrices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors

Abstract

The information shunting system is used to shunt information to the left or right by a given number of places during a clock period. It comprises two registers (1, 2) each with a number of storage cells(3) which are coupled via code lines(13i) each coupled to the inputs of a group of storage cells in each register(1, 2). The first information output(7) of each storage cell(3) of the first register(1) is coupled to the first information input (4) of a corresponding cell of the second register(2) etc., so that for each cell of each register(1, 2) each information input(4, 5, 6) is connected with a corresponding output(7, 8, 9).
FR7809664A 1978-03-31 1978-03-31 Information shunting system for digital processor - uses two registers and code lines between individual storage cells Granted FR2421441A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7809664A FR2421441A1 (en) 1978-03-31 1978-03-31 Information shunting system for digital processor - uses two registers and code lines between individual storage cells

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7809664A FR2421441A1 (en) 1978-03-31 1978-03-31 Information shunting system for digital processor - uses two registers and code lines between individual storage cells

Publications (2)

Publication Number Publication Date
FR2421441A1 true FR2421441A1 (en) 1979-10-26
FR2421441B1 FR2421441B1 (en) 1980-10-17

Family

ID=9206551

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7809664A Granted FR2421441A1 (en) 1978-03-31 1978-03-31 Information shunting system for digital processor - uses two registers and code lines between individual storage cells

Country Status (1)

Country Link
FR (1) FR2421441A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0377814A2 (en) * 1989-01-13 1990-07-18 International Business Machines Corporation Partial decode shifter/rotator

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3605024A (en) * 1970-06-01 1971-09-14 Goodyear Aerospace Corp Apparatus for shifting data in a long register

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3605024A (en) * 1970-06-01 1971-09-14 Goodyear Aerospace Corp Apparatus for shifting data in a long register

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
EXBK/74 *
NV8092/70 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0377814A2 (en) * 1989-01-13 1990-07-18 International Business Machines Corporation Partial decode shifter/rotator
EP0377814A3 (en) * 1989-01-13 1992-03-18 International Business Machines Corporation Partial decode shifter/rotator

Also Published As

Publication number Publication date
FR2421441B1 (en) 1980-10-17

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ST Notification of lapse