JPS5528191A - Memory unit - Google Patents

Memory unit

Info

Publication number
JPS5528191A
JPS5528191A JP10201678A JP10201678A JPS5528191A JP S5528191 A JPS5528191 A JP S5528191A JP 10201678 A JP10201678 A JP 10201678A JP 10201678 A JP10201678 A JP 10201678A JP S5528191 A JPS5528191 A JP S5528191A
Authority
JP
Japan
Prior art keywords
modules
transfer
period
information
page mode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10201678A
Other languages
Japanese (ja)
Inventor
Katsuhiko Aoki
Shigeo Kaneda
Toshihiko Sato
Yoshimi Tachibana
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10201678A priority Critical patent/JPS5528191A/en
Publication of JPS5528191A publication Critical patent/JPS5528191A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To enable the time sharing multiplex transfer for input and output with shorter period than the period of the address page mode, by continuously reading out or writing in the information of transfer block, through the independent operation of a plurality of memory modules.
CONSTITUTION: The memory unit 1 is provided with the memory modules 30 and 31, the module 30 is stored with the information belonging to the transfer blocks B0 and B2, and the module 31 is stored with the information belonging to the transfer blocks B1 and B3. Further, the registers 40 and 41 and the multiplexer 5 are provided according to the modules 31 and 32 to constitute the memory IC operationable for the modules 30 and 31 with the address page mode. Further, the period of the address page mode operation of the modules 30 and 31 is transferred with longer period than the information transfer period on the input and output information line 2, the address page mode is used for the modules 30 and 31 with separate parallel operation to shorten the information transfer period and to perform time sharing multiplex transfer.
COPYRIGHT: (C)1980,JPO&Japio
JP10201678A 1978-08-22 1978-08-22 Memory unit Pending JPS5528191A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10201678A JPS5528191A (en) 1978-08-22 1978-08-22 Memory unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10201678A JPS5528191A (en) 1978-08-22 1978-08-22 Memory unit

Publications (1)

Publication Number Publication Date
JPS5528191A true JPS5528191A (en) 1980-02-28

Family

ID=14315949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10201678A Pending JPS5528191A (en) 1978-08-22 1978-08-22 Memory unit

Country Status (1)

Country Link
JP (1) JPS5528191A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57123671A (en) * 1980-12-10 1982-08-02 Amp Inc Connector for flat cable
JPS5967887U (en) * 1982-10-28 1984-05-08 アンプ・インコ−ポレ−テツド printed circuit board socket
JPH01181137A (en) * 1988-01-14 1989-07-19 Nec Corp Storage unit
JPH0262141A (en) * 1988-08-29 1990-03-02 Fujitsu Ltd Inter-block transfer control system

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57123671A (en) * 1980-12-10 1982-08-02 Amp Inc Connector for flat cable
JPH0235428B2 (en) * 1980-12-10 1990-08-10 Amp Inc
JPS5967887U (en) * 1982-10-28 1984-05-08 アンプ・インコ−ポレ−テツド printed circuit board socket
JPH01181137A (en) * 1988-01-14 1989-07-19 Nec Corp Storage unit
JPH0262141A (en) * 1988-08-29 1990-03-02 Fujitsu Ltd Inter-block transfer control system
JPH0771092B2 (en) * 1988-08-29 1995-07-31 富士通株式会社 Block transfer control method

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