JPS56110150A - Parallel classification processing device - Google Patents
Parallel classification processing deviceInfo
- Publication number
- JPS56110150A JPS56110150A JP1274980A JP1274980A JPS56110150A JP S56110150 A JPS56110150 A JP S56110150A JP 1274980 A JP1274980 A JP 1274980A JP 1274980 A JP1274980 A JP 1274980A JP S56110150 A JPS56110150 A JP S56110150A
- Authority
- JP
- Japan
- Prior art keywords
- order
- input
- numerical values
- output
- classification
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/22—Arrangements for sorting or merging computer data on continuous record carriers, e.g. tape, drum, disc
- G06F7/24—Sorting, i.e. extracting data from one or more carriers, rearranging the data in numerical or other ordered sequence, and rerecording the sorted data on the original carrier or on a different carrier or set of carriers sorting methods in general
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/22—Indexing scheme relating to groups G06F7/22 - G06F7/36
- G06F2207/228—Sorting or merging network
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Image Processing (AREA)
Abstract
PURPOSE:To make the equipment small-sized and also execute the processing at a high speed, by arranging input signals in order which are adjacent to each other and are not arranged in order, by combining 2 kinds of classification cells at the next stage. CONSTITUTION:The binary numerical values which are stored in the respective shift registers 11-22 by a synchronizing signal input from the synchronizing signal line 100 are output in order from the high rank bit, respectively, and are provided to the parallel classification processing equipment 1. In this case, the respective classification cells 31, 21, etc. decide the combination of input signals which are input to them, respectively, arrange in order the numerical values corresponding to the input signals, and output them to the prescribed output signal lines. For instance, the three input/output classification cell 11 classifies the binary numerical values which are provided in order through the input signal lines 101-103, and outputs them to the signal lines 201, 202', 203' in order from the smallest numerical value. The two input classification cell 21 also classifies two numerical values and outputs them in the same way. In this way, the binary numerical values which have been provided to the equipment 1 are rearranged in order of size to output to the signal lines 201-212.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1274980A JPS56110150A (en) | 1980-02-05 | 1980-02-05 | Parallel classification processing device |
| US06/232,052 US4410960A (en) | 1980-02-05 | 1981-02-05 | Sorting circuit for three or more inputs |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1274980A JPS56110150A (en) | 1980-02-05 | 1980-02-05 | Parallel classification processing device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56110150A true JPS56110150A (en) | 1981-09-01 |
| JPS627579B2 JPS627579B2 (en) | 1987-02-18 |
Family
ID=11814059
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1274980A Granted JPS56110150A (en) | 1980-02-05 | 1980-02-05 | Parallel classification processing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56110150A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62200455U (en) * | 1986-06-13 | 1987-12-21 | ||
| KR102556154B1 (en) * | 2021-03-24 | 2023-07-19 | 대한플라테크 주식회사 | Continuous Extrusion Molding Apparatus capable of speed control |
-
1980
- 1980-02-05 JP JP1274980A patent/JPS56110150A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS627579B2 (en) | 1987-02-18 |
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