JPS5514765A - Counter circuit - Google Patents

Counter circuit

Info

Publication number
JPS5514765A
JPS5514765A JP8784478A JP8784478A JPS5514765A JP S5514765 A JPS5514765 A JP S5514765A JP 8784478 A JP8784478 A JP 8784478A JP 8784478 A JP8784478 A JP 8784478A JP S5514765 A JPS5514765 A JP S5514765A
Authority
JP
Japan
Prior art keywords
signal
counter
shift
supplied
signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8784478A
Other languages
Japanese (ja)
Other versions
JPS6242414B2 (en
Inventor
Hiroshi Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8784478A priority Critical patent/JPS5514765A/en
Publication of JPS5514765A publication Critical patent/JPS5514765A/en
Publication of JPS6242414B2 publication Critical patent/JPS6242414B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K21/00—Details of pulse counters or frequency dividers
    • H03K21/08—Output circuits

Abstract

PURPOSE:To secure the front and back shift for the counter output by the front an and back shift signals and with addition of a small-scale logic circuit to the general counter circuit. CONSTITUTION:Front-shift signal 15 is supplied through terminal 9 to 1st counter 1 possessing several units of the storage data input along with back-shift signal 14 supplied through terninal 8 respectively. And logic 1 and 0 are supplied to terminal 7 and 10 each. At the same time, signals 14 and 15 plus carry signal 17 of counter 1 are supplied to 2nd counter 2, and the signal stored in counter 1 is supplied via gate circuit 4 when signals 14 and 15 are active. The normal operation is given to counter 1 and 2 when signals 14 and 15 feature 0. And the back-shift action is given when signal 14 and shift signal 16 are set 1 with signal 1 set 0. Then the back-shift is made possible without inhibiting signal 17 only when signal 14 is 1 and via gate circuit 3 which uses signal 16 and 17 as the input.
JP8784478A 1978-07-18 1978-07-18 Counter circuit Granted JPS5514765A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8784478A JPS5514765A (en) 1978-07-18 1978-07-18 Counter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8784478A JPS5514765A (en) 1978-07-18 1978-07-18 Counter circuit

Publications (2)

Publication Number Publication Date
JPS5514765A true JPS5514765A (en) 1980-02-01
JPS6242414B2 JPS6242414B2 (en) 1987-09-08

Family

ID=13926195

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8784478A Granted JPS5514765A (en) 1978-07-18 1978-07-18 Counter circuit

Country Status (1)

Country Link
JP (1) JPS5514765A (en)

Also Published As

Publication number Publication date
JPS6242414B2 (en) 1987-09-08

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