JPS5620362A - Error information system - Google Patents

Error information system

Info

Publication number
JPS5620362A
JPS5620362A JP9577779A JP9577779A JPS5620362A JP S5620362 A JPS5620362 A JP S5620362A JP 9577779 A JP9577779 A JP 9577779A JP 9577779 A JP9577779 A JP 9577779A JP S5620362 A JPS5620362 A JP S5620362A
Authority
JP
Japan
Prior art keywords
signal
error
answer
information system
error information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9577779A
Other languages
Japanese (ja)
Inventor
Shuji Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP9577779A priority Critical patent/JPS5620362A/en
Publication of JPS5620362A publication Critical patent/JPS5620362A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received

Abstract

PURPOSE:To reduce signal lines in number by making it possible to report error generation, by inhibiting the return of an answer signal in response to the error generation in communication between asynchronous units. CONSTITUTION:On reception of a start signal, delay circuit 2 provides fixed-time delay and then FF4 is set, sending answer signal (b). Then, FF4 is supplied with start signal (a) as a clock signal and reset at the fall of signal (a). Next, NAND circuit 3 gates the set signal of FF4 with error signal E. Therefore, once an error is generated, FF4 is never set, so tht answer signal (b) will not be sent out.
JP9577779A 1979-07-27 1979-07-27 Error information system Pending JPS5620362A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9577779A JPS5620362A (en) 1979-07-27 1979-07-27 Error information system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9577779A JPS5620362A (en) 1979-07-27 1979-07-27 Error information system

Publications (1)

Publication Number Publication Date
JPS5620362A true JPS5620362A (en) 1981-02-25

Family

ID=14146905

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9577779A Pending JPS5620362A (en) 1979-07-27 1979-07-27 Error information system

Country Status (1)

Country Link
JP (1) JPS5620362A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61276051A (en) * 1985-05-31 1986-12-06 Fujitsu Ltd Data transmission control system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61276051A (en) * 1985-05-31 1986-12-06 Fujitsu Ltd Data transmission control system

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