JPS56160162A - Data transmitting system - Google Patents
Data transmitting systemInfo
- Publication number
- JPS56160162A JPS56160162A JP6366880A JP6366880A JPS56160162A JP S56160162 A JPS56160162 A JP S56160162A JP 6366880 A JP6366880 A JP 6366880A JP 6366880 A JP6366880 A JP 6366880A JP S56160162 A JPS56160162 A JP S56160162A
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- signal
- terminal device
- delay
- rise
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q9/00—Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
- H04Q9/14—Calling by using pulses
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Arrangements For Transmission Of Measured Signals (AREA)
- Dc Digital Transmission (AREA)
- Small-Scale Networks (AREA)
Abstract
PURPOSE:To eliminate a useless cycle, by transmitting a single pulse having a comparatively long duration prior to a transmission of a clock pulse from a data collecting station to a terminal device and then applying a resetting at the side of the terminal device. CONSTITUTION:A single pulse P1 having a comparatively long duration T1 is transmitted prior to a transmission of a clock pulse P2. Actually the output signal of a delaying circuit 20 becomes as shown in the figure (b) when a pulse sigal as shown in the figure (a) is supplied to the terminal device II from the data collecting station I. Then a counter divider 21 and a counter 22 are reset with a delay of time t1 to a rise of the pulse signal P1, and the output signal of a delaying circuit 25 becomes as shown in the figure (c). The gate circuit G is opened with a delay of time t2(t2>t1) to the rise of the signal P1. In such a way, the device II is put under a queuing state by the signal P1 transmitted from the station I.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6366880A JPS56160162A (en) | 1980-05-14 | 1980-05-14 | Data transmitting system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6366880A JPS56160162A (en) | 1980-05-14 | 1980-05-14 | Data transmitting system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56160162A true JPS56160162A (en) | 1981-12-09 |
Family
ID=13235950
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6366880A Pending JPS56160162A (en) | 1980-05-14 | 1980-05-14 | Data transmitting system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56160162A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04107196U (en) * | 1991-02-28 | 1992-09-16 | スズキ株式会社 | Vehicle drive sprocket shaft seal device |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4835484U (en) * | 1971-08-27 | 1973-04-27 | ||
JPS52109804A (en) * | 1976-01-09 | 1977-09-14 | Post Office | Data transmission system |
-
1980
- 1980-05-14 JP JP6366880A patent/JPS56160162A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4835484U (en) * | 1971-08-27 | 1973-04-27 | ||
JPS52109804A (en) * | 1976-01-09 | 1977-09-14 | Post Office | Data transmission system |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04107196U (en) * | 1991-02-28 | 1992-09-16 | スズキ株式会社 | Vehicle drive sprocket shaft seal device |
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