JPS536557A - Logic circuit - Google Patents

Logic circuit

Info

Publication number
JPS536557A
JPS536557A JP8060476A JP8060476A JPS536557A JP S536557 A JPS536557 A JP S536557A JP 8060476 A JP8060476 A JP 8060476A JP 8060476 A JP8060476 A JP 8060476A JP S536557 A JPS536557 A JP S536557A
Authority
JP
Japan
Prior art keywords
logic circuit
load
transistors
constituting
reduce
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8060476A
Other languages
Japanese (ja)
Inventor
Takeshi Takeya
Yasuo Omori
Nobuaki Ieda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP8060476A priority Critical patent/JPS536557A/en
Publication of JPS536557A publication Critical patent/JPS536557A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/096—Synchronous circuits, i.e. using clock signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To reduce the load capacity of clock signal, by constituting the load elements with the two transistors in series connection.
JP8060476A 1976-07-07 1976-07-07 Logic circuit Pending JPS536557A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8060476A JPS536557A (en) 1976-07-07 1976-07-07 Logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8060476A JPS536557A (en) 1976-07-07 1976-07-07 Logic circuit

Publications (1)

Publication Number Publication Date
JPS536557A true JPS536557A (en) 1978-01-21

Family

ID=13722922

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8060476A Pending JPS536557A (en) 1976-07-07 1976-07-07 Logic circuit

Country Status (1)

Country Link
JP (1) JPS536557A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49105438A (en) * 1973-02-07 1974-10-05
JPS509142A (en) * 1973-05-30 1975-01-30
JPS50113164A (en) * 1974-02-13 1975-09-05

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49105438A (en) * 1973-02-07 1974-10-05
JPS509142A (en) * 1973-05-30 1975-01-30
JPS50113164A (en) * 1974-02-13 1975-09-05

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