JPS5776633A - Signal processor - Google Patents

Signal processor

Info

Publication number
JPS5776633A
JPS5776633A JP15205280A JP15205280A JPS5776633A JP S5776633 A JPS5776633 A JP S5776633A JP 15205280 A JP15205280 A JP 15205280A JP 15205280 A JP15205280 A JP 15205280A JP S5776633 A JPS5776633 A JP S5776633A
Authority
JP
Japan
Prior art keywords
bit
shift register
significant digit
circuit
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15205280A
Other languages
Japanese (ja)
Other versions
JPS6367688B2 (en
Inventor
Shizuo Sugiyama
Yoshimune Hagiwara
Shigemichi Maeda
Takashi Akazawa
Masahito Kobayashi
Yasuhiro Kita
Yuzo Kida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Denshi KK
Hitachi Ltd
Original Assignee
Hitachi Denshi KK
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Denshi KK, Hitachi Ltd filed Critical Hitachi Denshi KK
Priority to JP15205280A priority Critical patent/JPS5776633A/en
Publication of JPS5776633A publication Critical patent/JPS5776633A/en
Publication of JPS6367688B2 publication Critical patent/JPS6367688B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/01—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising
    • G06F5/017—Methods or arrangements for data conversion without changing the order or content of the data handled for shifting, e.g. justifying, scaling, normalising using recirculating storage elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To eliminate the limitations of the bit length and bit arrangement of an input signal by arranging the bits of the input signal inversely of the bit arrangement inputted to a shift register when the least significant digit bit arrives as an initial bit. CONSTITUTION:When the least significant digit bit LSB comes first, an AND circuit 206 is selected by a control signal 22. Input data stored in a shift register 209 with the LSB at the beginning is transmitted to a data bus output switching circuit 210. When the data is outputted to a line 25, the control signal 22 permits switching so that the 2<0> of the data bus 25 is assigned to the bit SR15 of the register, and the 2<15> to the bit SRO. When the most significant digit bit MSB comes first, an AND circuit 205 is signified and the input data is stored in the shift register 209 being shifted successively from the SRO to SR15. In this case, a bus output switching circuit 210 sends the output, as it is, without changing the bit arrangement.
JP15205280A 1980-10-31 1980-10-31 Signal processor Granted JPS5776633A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15205280A JPS5776633A (en) 1980-10-31 1980-10-31 Signal processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15205280A JPS5776633A (en) 1980-10-31 1980-10-31 Signal processor

Publications (2)

Publication Number Publication Date
JPS5776633A true JPS5776633A (en) 1982-05-13
JPS6367688B2 JPS6367688B2 (en) 1988-12-27

Family

ID=15531990

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15205280A Granted JPS5776633A (en) 1980-10-31 1980-10-31 Signal processor

Country Status (1)

Country Link
JP (1) JPS5776633A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63265323A (en) * 1986-12-19 1988-11-01 Fujitsu Ltd Bit array converting system
US5138641A (en) * 1989-04-27 1992-08-11 Advanced Micro Devices, Inc. Bit residue correction in a dlc receiver
CN107534486A (en) * 2016-02-25 2018-01-02 松下电器（美国）知识产权公司 Signal decoding method, signal decoding apparatus and program

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55124036U (en) * 1979-02-20 1980-09-03
JPS55124036A (en) * 1979-03-16 1980-09-24 Meidensha Electric Mfg Co Ltd Exciter

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55124036U (en) * 1979-02-20 1980-09-03
JPS55124036A (en) * 1979-03-16 1980-09-24 Meidensha Electric Mfg Co Ltd Exciter

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63265323A (en) * 1986-12-19 1988-11-01 Fujitsu Ltd Bit array converting system
US5138641A (en) * 1989-04-27 1992-08-11 Advanced Micro Devices, Inc. Bit residue correction in a dlc receiver
CN107534486A (en) * 2016-02-25 2018-01-02 松下电器（美国）知识产权公司 Signal decoding method, signal decoding apparatus and program
CN107534486B (en) * 2016-02-25 2021-04-30 松下电器（美国）知识产权公司 Signal decoding method, signal decoding device, and recording medium

Also Published As

Publication number Publication date
JPS6367688B2 (en) 1988-12-27

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