GB1487706A - Data storage arrangement for buffering asynchronous input and output data streams - Google Patents
Data storage arrangement for buffering asynchronous input and output data streamsInfo
- Publication number
- GB1487706A GB1487706A GB465775A GB465775A GB1487706A GB 1487706 A GB1487706 A GB 1487706A GB 465775 A GB465775 A GB 465775A GB 465775 A GB465775 A GB 465775A GB 1487706 A GB1487706 A GB 1487706A
- Authority
- GB
- United Kingdom
- Prior art keywords
- store
- output
- input
- selections
- storage arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
1487706 Buffer storage systems PLESSEY CO Ltd 16 Jan 1976 [4 Feb 1975] 4657/75 Heading G4A A buffer storage system for use between asynchronous equipments comprises three stores S1-S3 and microprogrammed control units ISM, OSM responsive to "store full" and "no data" signals SF, ND indicating the status of each store to select one store at a time for input and a different store for output. The status indicators are set and reset by microprogram on start up, the beginning and end of an input process or output process as appropriate. An inhibit circuit IC produces signals IIS, IOS which are used by the output and input microprograms to ensure that only one process (input or output) can change store selection at a time by producing a corresponding change store selection signal CISS, COSS. The output process has priority over the input process if two store selection demands occur simultaneously. Detailed logic circuits for effecting the store selections with appropriate interlocks between selections are described.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB465775A GB1487706A (en) | 1976-01-16 | 1976-01-16 | Data storage arrangement for buffering asynchronous input and output data streams |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GB465775A GB1487706A (en) | 1976-01-16 | 1976-01-16 | Data storage arrangement for buffering asynchronous input and output data streams |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1487706A true GB1487706A (en) | 1977-10-05 |
Family
ID=9781336
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB465775A Expired GB1487706A (en) | 1976-01-16 | 1976-01-16 | Data storage arrangement for buffering asynchronous input and output data streams |
Country Status (1)
Country | Link |
---|---|
GB (1) | GB1487706A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3016269A1 (en) * | 1979-05-09 | 1980-11-20 | Int Computers Ltd | INFORMATION STORAGE DEVICE |
US4342097A (en) | 1980-02-28 | 1982-07-27 | Raytheon Company | Memory buffer |
EP0292287A2 (en) * | 1987-05-21 | 1988-11-23 | British Aerospace Public Limited Company | Asynchronous communication systems |
EP0483441A1 (en) * | 1990-11-02 | 1992-05-06 | STMicroelectronics S.r.l. | System arrangement for storing data on a FIFO basis |
-
1976
- 1976-01-16 GB GB465775A patent/GB1487706A/en not_active Expired
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3016269A1 (en) * | 1979-05-09 | 1980-11-20 | Int Computers Ltd | INFORMATION STORAGE DEVICE |
US4342097A (en) | 1980-02-28 | 1982-07-27 | Raytheon Company | Memory buffer |
EP0292287A2 (en) * | 1987-05-21 | 1988-11-23 | British Aerospace Public Limited Company | Asynchronous communication systems |
EP0292287A3 (en) * | 1987-05-21 | 1990-07-18 | British Aerospace Public Limited Company | Asynchronous communication systems |
EP0483441A1 (en) * | 1990-11-02 | 1992-05-06 | STMicroelectronics S.r.l. | System arrangement for storing data on a FIFO basis |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
732 | Registration of transactions, instruments or events in the register (sect. 32/1977) | ||
PCNP | Patent ceased through non-payment of renewal fee |