SU1396255A1 - Device for shaping relative bipulse signal - Google Patents

Abstract

The invention relates to telecommunications technology and can be used in digital transmission systems. The purpose of the invention — improving the reliability of the device — is achieved by simplifying. To do this, the device containing the triggers 1 and 2, the first clock bus 4, the first control bus 5, the second clock bus 6, the second control bus 7 and the output bus 8, additionally includes an EXCLUSIVE OR element 3. The output signal of the element 3 is is a relative bi-pulse signal in which in the middle of each clock interval there is a transition from one level to another, except for those clock intervals in which the clock signal is transmitted from the second control bus 7. 2 Il. about s

Description

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The invention relates to telecommunications technology and can be used in digital transmission systems.

The purpose of the invention is to increase the reliability of the work by simplifying.

Fig. 1 is an electrical circuit diagram of the device; figure 2 - timing charts.

The device for generating the relative bi-pulse signal contains the first 1 and second 2 triggers, element 3 EXCLUSIVE OR, the first and second inputs of which are connected to the outputs of the corresponding trigger I and 2. The synchronization input ;, the first trigger 1 is connected to the first clock bus 4 of the device. The enable input of the first trigger 1 is connected to the first control bus 5 of the device. The synchronizing input of the second trigger 2 is connected to the second clock bus 6 of the device. The enabling input of the second trigger 2 is connected to the second control bus 7, and the output of the EXCLUSIVE OR element is connected to the output bus 8 of the device.

The device works as follows.

The digital signal (FIG. 2a) from the first control bus 5 is fed to the enable input of the first trigger 1, the counting input of which receives a signal from the first clock bus 4 (FIG. 26 The first trigger 1 switches due to the transition from a low level to a high signal the first clock bus (fig. 26) if the information signal from the first control bus 5 (fig. 2a) has a high level at its enable input. Otherwise, the first trigger 1 does not switch. Similarly, the second trigger 2 switches under the influence of a low transition at DMS in you soky signal with the second clock bus 6, the inverse of the first clock otnoshenizo tire 4 (Fig. 2d), behaving

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go to its sync input if the sync signal (Fig. 2b) supplied to its enable input from the second control bus 7 has a high level. In the opposite case, the switch does not occur.

The output signals of the first and second 2 triggers (Fig. 2e, e) are fed to the inputs of the EXCLUSIVE OR 3 element, where they are summed modulo two. The output signal of the EXCLUSIVE OR 3 element (Fig. 2g) is a relative bi-pulse signal, in which in the middle of each clock interval there is a necessary transition from one level to another, except for those clock intervals in which the sync signal is transmitted from the second control bus 7. At the boundaries of the clock intervals, the transition from one level to another exists in the presence of 1 from the first control bus 5 (Fig. 2a) and is absent in the presence of O.

Claims (1)

Invention Formula A device for generating a relative bi-pulse signal containing the first and second triggers, characterized in that, in order to increase the reliability of operation, an EXCLUSIVE RSHI element is introduced, the first and second inputs of which are connected to the outputs of the corresponding trigger, the synchronizing input of the first trigger is connected to the first clock bus device , enabling the first trigger input - with the first control bus of the device; synchronizing input of the second trigger - with the second clock bus of the device; allowing the input of the second the first trigger is with the second control bus, and the output of the EXCLUSIVE OR element is with the output bus of the device. njTJTJTJnjnJTJTJTJ-LrLTLr e JlJTJTJlJnjnJlJTJTJ-LrLrL 2