SU1559400A1 - Device for switching clock frequency generator - Google Patents

Abstract

The invention relates to telecommunications and can be used to synchronously combine digital streams in automatic control and monitoring systems. The purpose of the invention is to improve the switching accuracy by eliminating the loss of a clock pulse when switching from one generator to another. The device contains the first delay element 1, the first 2 and second 3 inverters, the first 4 and second 5 elements AND, the element OR 6 and the control unit 7, containing the first 8 and second 9 D-flip-flops, the second element 10 delay, the element EQUIVALENCE 11, the element EXCLUSIVE OR 12, first 13 and second 14 inputs and output 15. The device has the first 16 and second 17 inputs of clock pulses and output 18. 2 Il.

Description

n

18

listened to $ ©

ABOUT

Phie.1

The invention relates to telecommunications and can be used to synchronously combine digital streams in automatic control and monitoring systems.

The aim of the invention is to improve the switching accuracy by f eliminating the loss of a clock pulse when switching from one generator to another.

Fig. 1 shows the functional diagram of the device j in Fig. 2, the time diagram of its operation.

The device (Fig "1") contains the first delay element 1, the first 2 and second 3 inverters, the first 4 and second 5 AND elements, the OR element 6 and the control unit 7, containing the first 8 and second 9 D-triggers, the second delay element 10, EQUIVALENCE element 11, EXCLUSIVE OR element 12 first 13 and second 14 inputs, as well as output 15 The device has the first 16 and second 17 inputs of clock pulses and output 18,

The output of the element OR 6 is connected to the output 18 of the device, the first input is connected to the output of the first element AND 4, the first input of which is connected to the output of the first inverter 2, the input of which is connected to the output 15 of the control unit 7 and the first input of the second element 5, whose output - one with the second input of the element OR 6, the first input 16 of the device is connected to the first input 13 of the control unit 7 and the input of the first delay element 1, the output of which is connected to the second input of the second element, as well as the second input 14 of the control unit 7. The second input 17 of the device is connected to the input of the second inverter 3, the output of which is connected to the second input of the first element AND 4. The second input 14 of the control unit 7 is connected to the second input of the EQUIVALENCE element 10 and the input of the second delay element 10, the output of which is connected to the first input of the EQUIVALENCE element And, the output of which is connected to the synchronous inputs of the first 8 and second 9 D-flip-flops, the first input 13 of control unit 7 is connected to the information input of the first D-flip-flop 8, the direct output of which is connected to the information input of the second D- three of the 9 and the first input of the EXCLUSIVE OR 12 element, the second input of which is connected to the forward output of the second D-flip-flop 9, and the output is connected by the output 1b of the control unit 7,

The switching device of the clock generators works as follows

The clock frequency signal PM-1 (FIG. 1) is fed to the first input 13.

block 7 control and information

the input of the first D-flip-flop 8, and from its output - to the information input of the second D-flip-flop 9. Signals at the outputs of the first 8 and second 9 D-flip-flops

depicted in FIG. 2d, e respectively

To the second input 14 of block 7 control receives the clock pulses of PM-1, delayed by half the period of their

on T / 2,

The signals from the outputs of D-flip-flops 8 and 9 are sent to the corresponding inputs of the EXCLUSIVE OR 12 element, in accordance with the logic of the element

5 EXCLUSIVE OR 12 at its output

a unit is always formed (fig. 2g), if at the input of the first delay element 1 on T / 2 there are clock pulses,

0 When the clock frequency pulse disappears in the PM-1 signal (fig. 2a, pulse 4), a unit potential is formed at the output of the element EQUIVALENCE 11 (fig. 2d), which prohibits writing information to D-flip-flops 8 and 9. At the same time, at the output of element 12 EXCLUSIVE OR zero potential is formed (Fig 2zh)

Thus, when there is a signal

0 la PM-1 () at the output 15 of the control unit 7, a single potential is formed that allows the passage of the PM-1 signal from the output of the first delay element 1 to T / 2 through the second

5 element AND 5 (FIG. 2i) at the output of the element OR 6 (FIG. 2n). In this case, at the output of the first inverter 2, a zero potential () is formed, prohibiting the passage of a clock signal

0 frequency of the PM-2 (fig, 2k) from the output of the second inverter 3 (fig, 2l) through the first element 4 (fig, 2m). Consequently, in the presence of a PM-1 signal at the output 18 of the device, this

with signal.

When the signal of the clock frequency of PM-1 disappears at the output 15 of the control unit 7, a zero potential is formed, and at the output of the first inverter

2 - single potential - allowing the passage of the clock frequency signal of the PM-2 from the output of the second inverter 3 to the output of the first element AND 4 and further through the element OR 6 to the output 18 of the device.

Thus, when the signal of the clock frequency of the PM-1 disappears, the output of the device automatically switches from the signal of the PM-1 signal to the signal of the PM-2 without loss of the clock frequency pulse.

Claims (1)

Invention Formula The switching device of the clock generators containing the control unit, the first inverter, the first and second elements AND, the OR element of which is connected to the output of the device, the first input is connected to the output of the first element And, the first input of which is connected to the output of the first inverter whose input is connected to the output of the control unit and to the first input of the second element I, the output of which is connected to the second input of the OR element, the first input of the device connected to the first input of the control unit, so that , with the aim of increase the switching accuracy by eliminating the loss of a clock pulse when switching from one generator to another, the first delay element and the second inverter, whose input is connected to the second input of the device, and the output connected to the second input of the first element, are added, the output of the first delay element is connected to the second the input of the second element And the second input of the control unit, and the input of the first delay element connected to the first input of the control unit containing the first and second D-flip-flops, the second element holder, an EXCLUSIVE OR element, and also the EQUIVALENCE element, the first input of which is connected to the output of the second delay element, whose input is connected to the second input of the EQUIVALENCE element and the second input of the control unit, the first input of which is connected to the information input of the first D-trigger, the synchronous input of which is connected to the output of the EQUIVALENCE element and to the synchronous input of the second D-flip-flop, whose information input is connected to the direct output of the first D-flip-flop and the first input of the EXCLUSIVE OR element, the second input of which It is connected to the forward output of the second D-flip-flop, and the output is connected to the output of the control unit.