SU444317A1 - Minimum selector - Google Patents

Description

one

The present invention relates to radio engineering and may be used in information processing devices.

The known selectors, which contain the delay line and the Matching scheme, are characterized by the impossibility of obtaining the output of the selector switches, in which the duration is equal to the duration of the input pulses.

The purpose of the invention is to restore the duration of the output signal to the duration of the input signal.

For this, the output of the specified coincidence circuit is connected via the first investor to the first inputs of the second and third coincidence circuits, and the output of the delay line is connected via a second inverter to the second input of the third coincidence circuit, and the outputs of the second and third coincidence circuits are connected to the inputs of the circuit OR, the output of which is connected to the second input of the second coincidence circuit and to the input of the third inverter.

The essence of the invention is that the selector circuit consisting of delay line 1 and circuit "AND 2 additionally introduced three inverters 3, 4 and 5, two circuits 6 and 7 and circuit" OR 8, and the output circuit "And 2 connected through the inverter 3 with the first output of the circuits "And 6 and 7. The outputs of circuits 6 and 7 are connected to the inputs of the circuit" OR 8, and the output

scheme "OR 8 is connected to the second input of the circuit 6 and through the inverter 5 with the output of the selector. The second input of the circuit 7 is connected via an inverter 4 with the output of the line delayed 1 and

with the second input of circuit 2.

FIG. 1 is a diagram of the selector; FIG. 2 - time range, showing the operation of the selector at various points. In the initial state, when there is no signal at the input, the selector at the outputs of inverters 3 and -4 will have unit levels that go to the inputs of circuit 7, and from the output of circuit 7 through the circuit OR8, the unit level goes to the second input of the circuit

6. At the output of the selector in this case, a zero level is generated (no signal).

When a pulse selector arrives at the input, the duration of which exceeds

delay line delay time, output

of circuit 2 a single impulse is generated

level that is inverted by inverter 3

and. enters the first inputs of circuits 6 and 7. On

the second input of circuit 7 from the output of investor 4

delayed delay

delay line 1 input name pulse zero

level In this case, the outputs of circuits 6 and

7 will generate pulses of zero

level, which through the circuit "OR" is fed to the input of the inverter 5 and to the second input of the circuit 6. At the output of the selector in this case a single level pulse will be generated.

As soon as the unit level impulse ends at the output of circuit 2, the first inputs of circuits 6 and 7 receive the potential of a single level from inverter 3, “o since the second input of circuit 7 receives a delayed input pulse of zero level, and the second INPUT of the 6-output circuit a zero level pulse, then a single level pulse will be maintained at the output of the selector until a delayed input pulse of a zero level arrives at the second input of circuit 7.

Upon completion, at the second input of Scheme 7, a zero pulse at the output of circuit 7 will generate a pulse of a single level, which through circuit 7 goes to the second input of circuit 6 and to the input of the inverter 5. A zero level will be established at the input of the selector.

Subject invention

A minimum duration selector containing a matching circuit, to the first input to which the input signal is fed directly, and to the second via a delay line, characterized in that, in order to restore the output signal duration to the input signal duration, the output of this coincidence circuit is connected through the first inverter with the first inputs of the second and T | retey coincidence circuits, and the output line

the delays are connected via a second inverter with a second input of the third coincidence circuit, and the outputs of the second and third coincidence circuits are connected to the inputs of the OR circuit, the output of which is connected to the second

the input of the coincidence circuit with the input of the third and the inverter.