SU1019606A1 - Device for discriminating pulse - Google Patents

Abstract

A DEVICE FOR ISOLATION OF A PULSE, containing two triggers, an inverter and an NAND element, the first input of which is connected to the output of an inverto; a, whose input is connected to the clock pulse bus and to the first input of the first trigger, the control pulse bus is connected to the first input of the second trigger, characterized in that, in order to increase speed while increasing the reliability, the control pulse bus is connected to the second input of the element AND-NOT, the output of which is connected to the second input of the first trigger, while the output of the first trigger is connected to the second input of the second trigger, the output of which is connected to the third input of the AND-NOT element.

Description

k /)

with

ABOUT)

about

Od

The invention relates to a pulse technique and can be used in computing and in digital measuring devices.

A device is known for extracting a pulse from a continuous pulse sequence containing two D-flip-flops and an IS-NOT element, the first input of which is connected to the output of the first D-flip-flop and the R- and D-inputs of the second D-flip-flop, whose output is connected to the output of the And element -NOT, the second input of the NAND is connected to C - the input of the first D-flip-flop, and the output of the second D-flip-flop is connected to the third input of the NAND-1 element.

The disadvantages of this device are the complexity and lack of speed due to the delay of the front of the output signal in the first D-flip-flop.

The closest technical solution to the invention is a device for extracting a single pulse containing a D-flip-flop, an RS-flip-flop, an AND-NIC and an inverter, whose input is connected to a source of clock pulses, the information input of a D-flip-flop is connected pulses, the control input is from the clock source, and the output is connected to the first input of the NAND element, the second input of which is connected to the inverter, and the output to the zero input of the RS flip-flop, the single input of which is connected to the control source a single signal, and a single output - with a zero input D-flip-flop 2.

A disadvantage of the known device is the low speed, complexity and not high enough reliability due to the presence of a D-flip-flop.

The aim of the invention is to increase the speed while increasing reliability.

The goal is achieved by the fact that in a pulse extraction device containing two flip-flops, an inverter, an AND-NOT element, the first input of which is connected to the output of the inverter, the input of which is connected to a clock pulse width and to the first input of the first trigger switch with the first input of the second trigger, the control pulse width is connected to the second input of the NAND element, the output of which is connected to the second input of the first trigger, while the output of the first trigger is connected to the second input of the second trigger, output which is connected to the third input of the AND-NOT.

FIG. 1 shows a diagram of the device; in fig. 2 - time diagrams of his work.

The device comprises a control pulse bus 1, a bus 2 clock pulses, an AND-NE element 3, an inverter 4, two RS flip-flops 5 and 6.

The device works as follows.

In the initial state, the output of the element AND-HE 3 and the output of the trigger 5 (the output of the device) contain high levels of voltage.

At the output of the trigger 6 there is a low voltage level. At the third input of the element IS-HE 3, connected via inverter 4 with a thickness of 2, the voltage level varies in antiphase with the voltage level on the busbar 2.

When a short control signal arrives at time tj along pin i, trigger 6 switches, since

At its second input, a high voltage level is present, and at the output of the trigger 6, a high voltage level appears, which is fed to the first input of the NAND 3. At the time i, the control signal at the output ends

0 element AND-NOT 3 a low voltage level appears, since the third input of the NE-3 element also contains a high level from the output of the inverter 4. At the output of the first trigger 5, the voltage level does not change, since its first The input level has a low voltage level of 2. When the voltage level on the busbar 2 changes at time tj, the trigger 5 switches and a dedicated pulse appears at its output.

0 is low, which, when it enters the second input of the second trigger 6, switches it, causing a low voltage level at its output. From the output of the trigger 6, a low voltage level, arriving at the first input of the element AND-HE 3, blocks its further operation upon receipt of the connecting pulses from the output of the inverter 4.

At time t on the busbar 2, a low voltage level appears, which, arriving at the first input of the trigger 5

0 switches it, causing high voltage at its output. The device has returned to its original state.

Upon receipt of subsequent pulses through bus 2 at time t, the trigger 5 does not change its state, since at its second input there is a high voltage level from the output of the AND-HE element 3.

On admission at time tg

Q of the next control signal repeats the operation cycle.

The use of the proposed device allows, in comparison with the known, to increase the speed due to the delay

5 only in one element of the IS-NOT RS-flip-flop, simplify and increase the reliability of the device by replacing the D-flip-flop with an RS-flip-flop.

N

: 5 e

"SJ

СЪ

Oq

Claims (1)

A device for isolating a PULSE containing two triggers, an inverter and an NAND element, the first input of which is connected to the output of the inverter, the input of which is connected to the clock bus and to the first input of the first trigger, the control pulse bus is connected to the first input of the second trigger, characterized in that, in order to improve performance while increasing reliability, the control pulse bus is connected to the second input of the AND-NOT element, the output of which is connected to the second input of the first trigger, while the output of the first iggera connected to the second input of the second flip-flop, whose output is connected to the third input of the AND-NOT. 9096101 FIG. 1