JPS56111944A - Parallel-series converter circuit - Google Patents

Parallel-series converter circuit

Info

Publication number
JPS56111944A
JPS56111944A JP1495280A JP1495280A JPS56111944A JP S56111944 A JPS56111944 A JP S56111944A JP 1495280 A JP1495280 A JP 1495280A JP 1495280 A JP1495280 A JP 1495280A JP S56111944 A JPS56111944 A JP S56111944A
Authority
JP
Japan
Prior art keywords
parallel
signal
circuit
input
series
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1495280A
Other languages
Japanese (ja)
Inventor
Haruo Nonaka
Osamu Amano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1495280A priority Critical patent/JPS56111944A/en
Publication of JPS56111944A publication Critical patent/JPS56111944A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00Parallel/series conversion or vice versa

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To realize a high-speed conversion with no time delay, by installing a parallel signal holding circuit plus a comparator to obtain a disagreement detection signal of the input/output signals of the said holding circuit at the front stage of a shift register that is inputted by a parallel signal and the delivers the series signal by the clock signal. CONSTITUTION:The circuit 13 to hold the parallel input signal plus a comparator 12 which detects a disagreement between the input and output signals of the circuit 13 through a comparison are installed at the front stage of the shift register which supplies the parallel signals A-C and then delivers the series signal via the clock signal. Thus the parallel input signals are set to the circuit 13 and the register 11 to perform a parallel-series conversion by the disagreement detection signal showing the changing point of the parallel input signal. In such way, a high-speed transmission is possible for the data with no delay of time since a parallel-series conversion is given at the moment when the signal level is changed.
JP1495280A 1980-02-09 1980-02-09 Parallel-series converter circuit Pending JPS56111944A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1495280A JPS56111944A (en) 1980-02-09 1980-02-09 Parallel-series converter circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1495280A JPS56111944A (en) 1980-02-09 1980-02-09 Parallel-series converter circuit

Publications (1)

Publication Number Publication Date
JPS56111944A true JPS56111944A (en) 1981-09-04

Family

ID=11875304

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1495280A Pending JPS56111944A (en) 1980-02-09 1980-02-09 Parallel-series converter circuit

Country Status (1)

Country Link
JP (1) JPS56111944A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01189219A (en) * 1988-01-22 1989-07-28 Matsushita Electric Ind Co Ltd Transition point detecting circuit for digital signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01189219A (en) * 1988-01-22 1989-07-28 Matsushita Electric Ind Co Ltd Transition point detecting circuit for digital signal

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