JPS63136238A - Microprogram control device - Google Patents

Abstract

PURPOSE:To easily analyze the microprogram steps by using an external memory means, a control means, an access address memory control means and a microprogram sequence control means. CONSTITUTION:When an access address memory mode is designated, a parity generating circuit 6 is invalidated and a 1st program stored in an external memory 1 is stored in a control memory 2 together with a parity bit. Then the 1st program is successively carried out. In this case, 1 is written to a parity bit part 11 of the address designated by a microprogram sequence control part 3 from an access address memory control part 4 through a signal line 106. Meanwhile a trouble detecting circuit 5 is invalidated and no parity error is detected. When a 2nd program is required, the 1st program of the memory 2 is stored in the memory 1 from a read register 7 together with the parity bit. Therefore the information on the parity bit equal to 1 is set to all addresses received accesses at the part 11 of the 1st program.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a microprogram control device, and more particularly to a microprogram control system (111!&) capable of storing addresses accessed during operation.

(Prior Art) A conventional microprogram control device a does not have a means for storing and retaining addresses accessed during its operation, or even if it does, it has an external state history device (hereinafter referred to as tracer memory). ), and stores accessed addresses sequentially.

(Problems to be Solved by the Invention) When developing and evaluating a microprogram, it is necessary to run a large number of test programs and confirm the correctness of all microprogram steps.

However, in conventional microprogram devices that do not have the above-mentioned conventional access address storage function, the address of the control memory accessed by the test program, that is, the microprogram step, must be logically clarified manually. However, the drawback is that it requires a lot of effort and time.

On the other hand, in conventional microprogram control devices equipped with an external tracer memory, due to the nature of the microprogram, if the same step is executed many times, the tracer memory will overflow, resulting in the desired function not being achieved, or In particular, due to control memory capacity limitations, so-called overlay program type microprogram control devices hold multiple program programs in external memory and execute them while sequentially storing them in control memory as needed. Since the same control memory address can be viewed multiple times by different programs, it is difficult to analyze and is not practical.

An object of the present invention is to provide an external storage means that holds control bits and check bits of a program to be stored in a control memory, and can store and read them from the control memory, and to instruct an access address storage mode. When the access address storage mode is specified, the upper check bit and failure detection of the control storage are disabled when the program is stored from the external storage means to the control memory, and the access address storage mode is set. The above drawback can be eliminated by writing information indicating that the above address has been accessed into the check bit of the control memory that is accessed during the operation of the control memory when instructed to do so, making the microprogram step easier to analyze. An object of the present invention is to provide a microprogram control device configured to perform the following steps.

(Problem 'f: Means for Solving) The present invention includes a microprogram system a-awn external storage means, a control (I[ll storage means), an access address storage control means, and a microprogram sequence control means. It was constructed as follows.

The external storage means is for holding a control bit section that controls each part of the device and a parity bit section that performs a parity check.

The control storage means is for storing the control bit section and the parity bit section from the external storage means (1) or for reading them into the external storage means.

The access address storage control means instructs the access address storage mode, and when the access address storage mode is specified, removes parity bits when storing a program from the external storage means to the control storage means, and detects a failure in the control glIll storage means. This is a reminder to invalidate the .

The microprogram sequence control means is for writing information indicating that the corresponding address is accessed to the parity bit part of the control storage means during operation of the control storage means when the access address storage mode is instructed. It is.

(Example) Next, the present invention will be explained with reference to the drawings.

Is the M1 diagram a microprogram system according to the present invention? FIG. 2 is a block diagram showing one embodiment of the n device.

In FIG. 1, l is an external storage device, 2 is a control storage device, and 3 is a control storage device.
4 is a microprogram sequence control section, 4 is an access address storage control section, 5 is a failure detection circuit, 6 is a parity bit detection circuit, and 7 is a bladder extraction register.

In FIG. 1, the external memory device fftl includes a rounding control bit section 10 for controlling the device valley, and a parity bit s (initial value is 0) for performing a parity check.
A microprogram consisting of the following is stored, and the signal lines 101 and 102 are all connected to the memory 2 of the system. Microprogram sequence system @1 capital 3 is 1 shift ff of address field inside control bit part 1 (),
The address of the next microprogram to be executed is provided to the control memory 2 through the signal line 103 and through the signal line 1.04.

The access address storage control unit 4 applies the access address storage mode' to the failure detection circuit 5 and the parity bit detection circuit 6 through the signal line 105, respectively, and disables failure detection and parity generation. The control bit section 10 inside the control memory 2 is sequentially outputted to the successive register through signal lines 103, 11) 7 under the control of the microprogram sequence control section 3, and is outputted to the successive register through signal lines 103 and 11).
to the device's control circuitry (not shown). The control signal slO is applied to the failure detection circuit 5 together with the parity bit unit 11 during normal operation, and generates a parity error signal on the signal line 120 when a failure is detected.

At the same time, in the access address storage mode, 1'' is written from the access address storage control section 4 to the parity bit section 11 of the address designated by the microprogram sequence control section 3 through the signal line 1 (16).

Furthermore, the contents of the control unit 0!2 are read out to the external storage device through the signal line 110.

In FIG. 1, in this device, during normal operation, the program stored inside the external storage device yt1 is generated by the parity generation circuit 6, and then stored in the control memory 2 together with the parity, according to the control of the microprogram sequence control section 3. , are executed sequentially. Need to store the next program':)7? , the nuclear detonation program is searched for in the external storage device 1 and similarly stored in the control storage 2 and executed. During execution, the contents of the control memory 2 are parity-checked by the failure detection circuit 5, and in the event of a failure, the signal line 1 is
21) generate a parity error signal on the

Next, when the access address storage mode is specified, the parity generation circuit 6 is disabled, so the first program inside the external storage device 1, including the parity bit, is stored in the control storage 2. executed sequentially. At this time, 1'' is written into the parity bit section 11 of the address specified by the microprogram sequence control section 3 from the access address storage control section 4 through the signal line 1 ( ) 6. During this time, the failure detection circuit 5 is disabled, so no parity error is detected.

When it becomes necessary to execute the second program, the first program inside the control memory 2 including the parity bit is sequentially output from the read register 7 to the external storage device yi1 through the signal lines 109 and 11(). is stored. Even if the first program is needed again, the first program is re-stored from the external storage device 1 to the control memory 2 in the same way as above, so that are accessed while the device is in operation, and information of harness bit=1 is set in all addresses.

(Effects of the Invention) As explained above, the present invention enables the evaluation of microprogram steps to be performed with less hardware by displaying all microprogram steps actually executed using a parity pin even in an overlay program type device. This has the effect of making it easy to know.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a microprogram control device according to the present invention. l...External storage device 2...Control memory 3...
Microprogram sequence control unit 4...Access address storage control unit 5...Failure detection circuit 6...Harness bit generation circuit 7...Read register

Claims (1)

[Claims] an external storage means for holding a control bit part for controlling each part of the device and a parity bit part for performing a parity check; and an external storage means for storing the control bit part and the parity bit part from the external storage means; control storage means for reading to the control storage means; instructing an access address storage mode, and generating a parity bit when storing a program from the external storage means to the control storage means when the access address storage mode is specified; and access address storage control means for disabling failure detection of the control storage means; and an access address storage control means for disabling failure detection of the control storage means; and a parity bit section of the control storage means applied to the parity bit portion of the control storage means during operation of the control storage means when the access address storage mode is instructed. 1. A microprogram control device comprising: microprogram sequence control means for writing information indicating that an address has been accessed.