JPH02252029A - Function element testing instrument - Google Patents

Abstract

PURPOSE:To prevent each buffer memory from being increased at its storage capacity by allowing a full coincidence detecting circuit to detect the heads of response output signals from all function elements to generate a reading address, and controlling the full coincidence detecting circuit through an overflow detector. CONSTITUTION:When the heads of response outputs from respective function elements DUT1 to DUTN to be tested responding to a test pattern signal supplied from a pattern generator 100 are detected, respective writing address generators 600A to 600N are started and the outputs of the elements DUT1 to DUTN are written in buffer memories BF1 to BFN. A reading address generator 800 is controlled by the full coincidence detecting circuit 700 in accordance with the detection of respective heads and the contents of respective memories BF1 to BFN are read out to test the elements DUT1 to DUTN by comparing the read contents with an expected pattern signal. The circuit 700 is forcedly turned to a full coincidence detecting state through a control coincidence signal generator 20 before the overflow of the memories BF1 to BFN. Thereby, each buffer memory can be prevented from being increased at its storage capacity.

Description

DETAILED DESCRIPTION OF THE INVENTION "Field of Industrial Application" The present invention relates to a functional element testing device for determining and testing the quality of functional elements such as microcomputers or IC cards incorporating microcomputers.

``Prior art'' A functional element with a microcomputer built into one semiconductor chip;
There are functional elements such as C cards.

Since these functional elements are microcomputers, they have arithmetic processing capabilities and can perform complex operations.

Conventionally, an apparatus having a structure as shown in FIG. 2 has been used to test the quality of such functional elements.

In the figure, 100 is a pattern generator, DIITI~DLITN
300A to 30ON indicate a device under test, 300A to 30ON a buffer memory, 400 a pass/fail judge, 500A to 50ON a coincidence detector, and 600A to 60ON a write address generator.

A test pattern signal is applied from the pattern generator 100 to the devices under test DIIT and DtlTN.

Coincidence detectors 500A to 50ON have each device under test DOT.
+ - These coincidence detectors 500A to 50ON, which perform the operation of detecting whether or not the first data of the response output signal is output from DIITN, are connected to the devices under test DIIT+ to □
When detecting that the DUTs have outputted data representing the beginning of the response output signal, the write address generator 60OA=
Activate -60ON, buffer memory BF,
-BF, each write address is assigned separately to each buffer memory BF.

~BF, respectively, the device under test DOT, ~DIIT,
Writes the response output signal.

700 indicates an all-match detector. This total loss detector 700
is, all the coincidence detectors 5008 to 50ON are the device under test θ
When it is detected that the first data has been output from lIT+ to DOT, the full match detector 700 detects this state and activates the read address generator 800.

When the read address generator 800 is activated, writing and reading are performed alternately in the buffer memories BP and -BFN.

Read addresses are all buffer memories BF, ~BF,
Commonly given to all buffer memories B
F1''''B FN is read out in order from the first address.

The response output signals of each device under test DOT, ~DUT, read from the buffer memories BF, -BF, are sent to the pass/fail determiner 4.
00 and is compared with a common expected value pattern to determine pass/fail.

"Problem that the invention attempts to solve" With conventional testing equipment of this type, 1. Yo buffer memory BF.

~BF has a capacitance capable of taking in all of the response output signals output from each of the devices under test DIIT and ~DUTH. Therefore, a large storage capacity is required.

Furthermore, the response speeds of the devices under test DtlT and -DUTN vary. The larger the time difference between when the earliest element starts outputting the first data and when the latest element outputs the first data, the buffer memory BF is increased accordingly.

~The storage capacity of BF must also be increased.
In other words, if the earliest element has finished outputting all response output signals and the latest element has not yet output the first data,
Since the buffer memory that takes in the response output signal of the element will continue to be written to, it is necessary to have a correspondingly large storage capacity.

Furthermore, when the storage capacity of the buffer memories 500A to 50ON is increased, the test is performed by reading out everything from the first address to the last address, which also has the disadvantage that the time required for the test becomes longer.

"Means for Solving the Problem" The present invention includes a plurality of leading data detectors each detecting the leading data representing the beginning of a response output signal outputted from a plurality of functional elements, and a plurality of leading data detectors provided for each functional element. When the first data detector detects the first data from the output of each functional element, a write address generator is activated by the detection output signal, and when this write address generator is activated, each of the above functional elements a plurality of buffer memories for storing response output signals, an all-match detector for detecting that all functional elements have outputted the first data, and an all-matching detector for detecting that all the functional elements have outputted the first data. a read address generator that is activated by the detection of the read address signal and provides a common read address signal to multiple buffer memories, and a common expectation that each data read from the multiple buffer memories according to the read address generated by this read address generator A pass/fail judge that compares with the value pattern and determines whether there is a match or no match, and a full match detector that does not detect a full match.
An overflow detector that detects that the write address of the buffer memory that is taking in the response output signal of the first element approaches the final address, and a buffer memory that this overflow detector is writing the response output signal of the first element. a force-fail signal generator that is activated by detecting that the write address of each buffer memory approaches the final address and provides a forced match signal to the all-match detector; and an address initialization circuit that detects the write address and returns the write address to the first address at the next write timing.

According to the functional device testing device of the present invention, in a state where the full match detector has not yet detected a full match, it is detected that the address of the buffer memory to which the response output signal of the element is written is approaching the final address. Overflow detector: When this overflow detector detects that the buffer memory is about to overflow, it forcibly activates the all match detector and starts reading, and when the overflow is reached, the address given to the buffer is changed to the first address. Since the new data is rewritten by overwriting the old data, the storage capacity of the buffer memory can be reduced.

In other words, the storage capacity of the buffer memory does not need to have the capacity to capture all of the response output signals output from the functional element under test, and from the time when the earliest element that occurs regularly outputs the first data, the latest element outputs the first data. It is sufficient to have the number of addresses written during the time difference until outputting the first data.

Therefore, according to the present invention, the storage capacity of the buffer memory can be reduced.

Furthermore, even if the device under test includes an element that does not output a response output signal for a long time, the all-coincidence detection circuit is forcibly activated just before the buffer memory of the element overflows, so there is no possibility that a defective element is included. However, the response output signal of a normal element is not damaged, so no time is wasted during the test, and the test can be performed efficiently.

"Embodiment" FIG. 1 shows an embodiment of the present invention. In Figure 1,
Components corresponding to those in FIG. 2 are designated by the same reference numerals.

The present invention includes an overflow detector 10 and a forced match signal generator 20 that is activated by the detection signal when the overflow detector 10 detects that any of the buffer memories approaches overflow. , address initialization circuits 30A to 30 that return the write address to the first address when the write address given to each buffer memory BF, -BFN reaches the final address.
It is characterized by a configuration in which an ON is provided.

The overflow detector 10 includes each coincidence detector 5008-5.
In addition to taking in the match detection output of 0ON and monitoring whether or not all matches have been achieved, each write address generator 600A to 600
The write address signal output from 0ON is taken in and each write address is monitored. Among the write addresses, an In address that is close to the final address 1/S is detected, and this detection signal is used as a forced match signal. The signal is applied to a generator 20 to generate a forced match signal.

The forced match detection signal outputted from the forced match signal generator 20 is applied to the full match detector 700, which forcibly generates a full match detection signal.

When the all match detection signal is generated in this way, the read address generator 800 is activated, and each buffer memory BF,
-BF, is given the read at1nos.

In this example, an address controller 40A=4ON is provided for each buffer buffer BFr-BFN, and this address controller 40
This shows a case where a write pulse and a read address are supplied to each buffer memory BF, -BF through A-4ON. Writing and reading are performed alternately, and writing and reading are executed. One cycle passes.

In the present invention, address initialization circuits 30A to 3ON are further provided in each address control π unit 40A to 4ON.

This address initialization circuit 30A-3ON detects that the write at 1/s given to each buffer memory BF, = BF has reached the final at 1/s (5), and if it is written at the next write timing. Performs an operation to return the included address to the first address.

By initializing the write address T/S in this manner, the storage capacity of the buffer memories BF, -BF can be reduced.

In other words, normally, when all of the mechanical elements I) UT1~[1LIT, finish outputting the first data, the full match detector 700 detects all matches among the match detectors 500A to 50ON, and starts the read address generator 800. and buffer memory B
Start reading F l-B F N.

When this reading is started, the data at the read address becomes unnecessary data. Therefore, reading is started,
By returning the write address to the first address after sequential reading from the first address, the same memory cell can be used repeatedly and the storage capacity can be used effectively. Therefore, a large amount of data can be processed with a small memory of one pair of pants.

Furthermore, in this invention, since the overflow detector 10 and the forced coincidence signal generator 20 are provided, the functional element under test DIIT
, ~DIIT, and even if the defect continues to prevent full match detection, the overflow detector 10 detects just before the write address overflows, and uses this detection signal to detect full match. Vessel 7
After forcing the match detection signal to 00 and activating the read address generator 800, the address initialization circuit 30A
~3ON detects that the write address has reached the final address, and returns the write address to the first address at the next write timing after this detection, so there is a defective product and the first data is not output. Even if the buffer memory of the element reaches the final address and the write address is initialized, the originally written data has already been read, so data corruption is avoided.As a result, each buffer memory BF, −
The storage capacity of the BFH may be equal to or slightly larger than the number of addresses that are accessed within the maximum value of the time difference between the earliest element and the latest element that outputs the first data. ” As described above, according to the present invention, the buffer memory B F
Since r~BF can be configured with a small capacity memory, the devices under test DIITI~DUTN can be tested at - times.
Even if a large number of parts are used, the cost can be suppressed and the product can be manufactured at a low cost.

[Brief explanation of drawings]

FIG. 1 is a block diagram for explaining an embodiment of the present invention, and FIG. 2 is a block diagram for explaining a conventional technique. 10 overflow detector, 20: forced match signal generator, 30A to 3 ON: i) address initialization circuit,
100: Pattern generator, 200: Device under test, BF
, -BF,: Buffer memory, 400: Pass/Fail determiner, 5
008~50ON match detector, 60OA~6Q
ON: 8 including 71' and 7. Generator, 700: All match detector, 800: Readout at 1/s generator.

Claims (1)

[Claims] (1) A. A test pattern signal is given to each device under test, which is equipped with an arithmetic processing function and consists of an IC-based functional element, and this response output signal is compared with an expected value pattern signal, and the result of the comparison is B. A plurality of leading data for detecting each of the leading data representing the beginning of response output signals outputted from the plurality of functional elements; C. a write address generator provided for each functional element and activated by the detection output signal when the leading data detector detects leading data from among the output signals of each functional element; , D. A plurality of buffer memories that sequentially store the response output signals of each of the functional elements at each address generated when the write address generator is activated, and E. All of the functional elements store the first data. F. A full match detector that detects that all the functional elements have outputted the first data; a read address generator that provides a read address generator; and H, an overflow detector that detects that the write address of the buffer memory to which the response output signal of the functional element is written is approaching the final address in a state where the full match detector does not detect the full match state; I. This overflow detector is activated by detecting that the write address of the buffer memory to which the response output signal of the functional element is written is approaching the final address, and sends a forced match signal to the all match detector. A forced match signal generator that gives J, an address initialization circuit that detects when the write address of each buffer memory reaches the final address and returns the write address to the first address at the next write timing. The constructed functional device testing device.