JP2690910B2 - Control storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A control storage device for relieving an error is provided with a plurality of identical microprograms composed of microinstructions having an error detection code for the purpose of shortening access time. Error detection for each of the plurality of microinstructions read out from each of the plurality of modules and the control storage unit stored in each of the modules,
An error detection / selection unit that selects and retrieves a smaller number of microinstructions than the plurality of microinstructions in order from the one in which no error is detected according to the detection result, and the microinstruction retrieved by the error detection / selection unit. A bit-by-bit vote and a voter that generates a single microinstruction and repairs errors. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control storage device, and more particularly to a control storage device that performs error relief. In a microprogram-controlled computer system, a microprogram is stored in a control storage device, and microinstructions forming the microprogram are sequentially read from this control storage device, and various controls are performed based on the microinstruction. . If the read microinstruction has an error, an erroneous control is performed. Therefore, an error is remedied to prevent this. [Prior Art] FIG. 5 is a block diagram showing an example of a conventional control storage device. In the figure, instructed by the address supplied from the address register 10, a micro instruction is read from the micro program of the control storage unit 11 and stored in the data register 12. An error correction code (ECC) capable of 1-bit error correction and 2-bit error detection is added to the microinstruction. The microinstruction output from the data register 12 is supplied to the error detection / correction unit 13, where the error detection and error correction processing (ECC processing) by the error correction code is performed, and thereafter the microinstruction is stored in the data register 14. From there, it is supplied to the connected decoder or the like via the terminal 15. In the case of a branch micro instruction, the branch destination address is supplied to the address register 10. The address register 10 receives a next address or an interrupt address from the terminal 16. [Problems to be Solved by the Invention] In the conventional device, since the error detection / correction unit 13 performs the ECC processing, the ECC processing time is added, the control storage access time becomes long, and the branch micro instruction is also used. There is a problem that it takes time to determine the branch destination address and the processing becomes slow. The present invention has been made in view of the above points, and an object of the present invention is to provide a control storage device that requires a short access time. [Means for Solving Problems] A control storage device according to the present invention is a control storage unit in which a plurality of modules (24a to 24d) store mutually identical microprograms each composed of a microinstruction having an error detection code ( 24) and an error of each of the plurality of micro-instructions read from each of the plurality of modules (24a to 24d) is detected, and in accordance with the detection result, an error is not detected. The error detection and selection unit (25,26,27) that selects and retrieves a smaller number of micro-instructions and the micro-instruction that is extracted by the error detection and selection unit (25,26,27) are voted in bit units. And a voting section (40) for generating a single micro instruction and repairing an error. [Operation] In the present invention, the same microprogram is stored in the control storage section (24) in a multiplexed manner, and the selection section (corresponding to the error detection result of each of the plurality of microinstructions read from the selection section ( 25, 26, 27) selects a predetermined number of micro-instructions, and a voting section (40) repairs the predetermined number of micro-instructions in bit units. Since simple error detection requires almost no time, and microinstruction selection and voting take almost no time, the access time is short even if error relief is performed, and high-speed access is possible. [Embodiment] FIG. 1 shows a block diagram of an embodiment of a control storage device of the present invention. In the figure, each of the terminals 20a, 20b, 20c receives an interrupt address from a program, a console, another system, etc.,
These are selected by the interrupt command selector 21 and supplied to the service pointer register (SP register) 22. In addition to this, the SP register 22 is supplied with a branch address and the next address from the incrementer 23. The SP register 22 stores any one of these addresses, and its output address is supplied to the control storage unit 24. To be done. The control storage unit 24 includes four modules 24 having the same configuration.
It consists of a to 24d. The same microprogram is redundantly stored in each of the modules 24a to 24d, and the same microinstruction is read from these modules 24a to 24d by the address from the SP register 22. A 1-bit parity code for error detection is added to the microinstruction. The microinstructions A to D read from the modules 24a to 24d are service sense registers (SS registers), respectively.
25 and the error detection and repair control unit 26. The SS register 25 is a micro instruction A from each of the modules 24a to 24d.
Each of D to D is stored and supplied to the repair selection unit 27. The detection and repair control unit 27 performs an exclusive OR operation on all bits of the microinstructions A to B to perform a parity check, and generates a repair code VC as shown in FIG. 2 to generate a repair selection unit. Supply to 27. In FIG. 2, "-" in the module error status column indicates no error, "1" indicates error, and the repair code VC column indicates the value. The repair selecting section 27 is composed of selectors 28, 29, 30 as shown in FIG. The selector 28 selects the microinstruction A from the terminal 31 when the repair code VC is "0", "1", "2", and selects the microinstruction B from the terminal 32 when the code VC is "3". Output as microinstruction V0 from terminal 35. Similarly, the selector 29 selects the micro instruction B when the code VC is "0" or "1", the micro instruction C from the terminal 33 when the code VC is "2" or "3", and selects the micro instruction from the terminal 36. Output as V1. Selector 30 has micro instruction C and code VC when code VC is 0.
Is "1", "2", "3", the microinstruction D from the terminal 34 is selected and output from the terminal 37 as the microinstruction V2. This rescue selected state is also shown in FIG. The voting unit 40 votes each microinstruction V0, V1, V2 bit by bit as shown in FIG. 4 to generate a rescued microinstruction OUT. That is, the following calculation is performed in bit units. OUT = V0 ・ V1 ＋ V1 ・ V2 ＋ V2 ・ V0 The microinstruction OUT output from this voting unit 40 is supplied from the terminal 41 to the subsequent decoder and the like, and when the microinstruction OUT is a branch, the branch destination address is supplied to the address register 22. To be done. Here, the error detection of the micro-instruction requires almost no time because it is an exclusive OR operation by hardware using a parity code, and the rescue selecting unit 27 and the voting unit 40 are also configured by hardware and take almost no time. Does not need Therefore, there is no increase in access time due to error relief,
High-speed access becomes possible. [Advantages of the Invention] As described above, according to the control storage device of the present invention, it is possible to prevent the access time from becoming long due to the error relief, and to shorten the access time to enable high-speed access, which is extremely useful in practice. It is useful.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of an embodiment of a control storage device of the present invention, FIG. 2 is a diagram for explaining a repair code and repair selection operation, and FIG. 3 is a repair selection unit. FIG. 4 is a circuit diagram of an embodiment of the present invention, FIG. 4 is a diagram for explaining voting by the voting recovery unit, and FIG. 5 is a block diagram of an example of a conventional device. In the figure, 22 is a service pointer register, 24 is a control storage unit, 24a to 24d are modules, 25 is a service sense register, 26 is an error detection and repair control unit, 27 is a repair selection unit, and 40 is a voting unit.

Claims (1)

(57) [Claims] Multiple identical microprograms composed of microinstructions with error detection code are stored in multiple modules (24a
~ 24d) The control storage unit (24) stored in each of them and the plurality of micro instructions read from each of the plurality of modules (24a to 24d) are subjected to error detection, and the error is detected according to the detection result. The error detection and selection unit (25, 26, 27) for selecting and extracting a smaller number of micro-instructions than the above-mentioned plurality of micro-instructions in order from the undetected one, and the error detection and selection unit (25, 26, 27). ), A vote storing unit (40) for generating a single microinstruction for each bit of the microinstruction fetched in (1) and performing error relief.