JPH0553934A - Bus line monitoring system - Google Patents

Abstract

PURPOSE:To easily acquire the information of a memory for trace from an external device even when a CPU is break down. CONSTITUTION:This computer system is formed by connecting a DMA 3 and a communication control interface 7 to a bus line 2 led out of a CPU 1 and connecting an external device 9 to the communication control interface 7, and the communication control interface 7, bus monitoring means 11-13 and memory 15 for trace are connected to the bus line 2 at least. When operating the CPU 1, the bus monitoring means 11-13 writes trace information from the external device 9 to the memory 15 for trace in the case of executing the data input/ output instruction of the CPU 1 on the bus line 2 and when the CPU 1 is breakdown, the external device 9 reads the trace information preserved in the memory 15 for trace through the communication control interface 7 and the monitoring means 11-13.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus line monitoring system used in a computer system for high-speed data transfer with an external device using a CPU, a DMA, etc., and particularly to a data collecting means when the CPU is down. Relates to an improved bus line monitoring system.

[0002]

2. Description of the Related Art This type of computer system is shown in FIG.
As shown in, D is placed on the bus line 2 derived from the CPU 1.
An MA (direct memory acces) 3, a memory 4, a peripheral I / O 5 and an input / output interface 6 are connected, and a communication control device 9 as an external device is connected to the bus line 2 via a communication control interface 7. There is. The CPU 1 executes control of all the components based on a predetermined program, and the DMA 3 is a CPU
1 and the bus line 2 are shared, the data transfer of the memory information is performed between the memory 4 and the communication control device 9 without going through the CPU 1. 8 is RAS (reliability: reli
ability, operability: availability, maintainability: serviceabi
lity) unit, which has a hardware error diagnosis function such as a memory parity error, and stores an error address and the like.

Therefore, in the computer system as described above, the CPU 1 manages the communication control interface 7 based on the program and also manages the data trace and the like, and fetches the memory information from the communication control device 9 and The memory information is transmitted in response to a data request from the communication control device 9.

That is, when memory information is obtained from an external device, for example, the communication control device 9, the CPU 1 controls the communication control interface 7 to connect the communication control device 9 to the communication control interface 7, and the communication control device 9 is connected. From the outside via the communication control interface 7 and the bus line 2 to obtain memory information from the outside. Regarding the memory information stored in the memory 4 inside the system,
The CPU 1 reads the memory information from the memory 4 and transmits it to the communication control device 9 via the bus line 2 and the communication control interface 7.

[0005]

However, in the above computer system, since the CPU 1 is responsible for all control functions, the communication control interface 7 is controlled when, for example, the CPU 1 is in a failure or abnormal state. It becomes impossible to obtain memory information from the outside. Further, if the CPU 1 stops while occupying the bus line 2, other necessary constituent functions cannot access the bus line 2.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a bus line monitoring system in which an external device can easily obtain memory information even when the CPU is down.

Further, another object of the present invention is to release the bus line occupation by the CPU and the DMA and to easily obtain memory information from a memory connected to the bus line from an external device. To provide.

[0008]

First, in order to solve the above-mentioned problems, the invention according to claim 1 is such that a DMA and a communication control interface are connected to a bus line derived from a CPU, and the communication control interface is externally connected. In a computer system in which devices are connected, at least the communication control interface, bus monitoring means and trace memory are connected to the bus line, and the CP
During the operation of U, the bus monitoring unit writes the trace information from the external device to the trace memory when it determines that the CPU is executing the data input / output instruction from the bus line,

When the CPU is down, the external device is
This is a bus line monitoring system for reading the trace information stored in the trace memory via the communication control interface and the bus monitoring means.

Next, the invention according to claim 2 adds bus release control means to the invention according to claim 1,
When the address set by the external device coincides with the address of the CPU by the bus release control means, the operation of the CPU and the DMA is stopped to release the bus line, and the external device transmits the bus via the bus monitoring means. This is a bus line monitoring method for accessing information such as memory and I / O connected to the bus line.

[0011]

Therefore, according to the invention corresponding to claim 1, by taking the above means, when the trace information including the trace memory address is transmitted from the external device,
The bus monitoring means monitors the address and data of the CPU on the bus line, and when it is detected that the data input / output instruction of the CPU is being executed when the CPU address is the same as the trace memory address, the trace information is displayed. The external device stores the data in the trace memory, while the external device reads the trace information stored in the trace memory through the communication control interface and the bus monitoring means, so that the external device can access the CPU when the CPU is down. Trace information can be retrieved without it.

Next, in the invention according to claim 2, the bus release control means sets the address and CP set by the external device.
Since the bus line is released by stopping the operations of the CPU and the DMA while checking the address of U, the information such as the memory and I / O connected to the bus line from the external device via the bus monitoring means. Can be accessed.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIG. In the figure, the same parts as those of the conventional computer system (FIG. 3) are designated by the same reference numerals and detailed description thereof will be omitted.

That is, this computer system is
A bus monitoring interface 11 and a trace control means 12 are newly provided between the bus line 2 and the communication control interface 7. This bus monitoring interface 1
1 determines whether it is an instruction fetch cycle of the CPU 1 or a data input / output instruction to the memory 4 or I / O, and when executing this data input / output instruction, a trace information write command is sent from an external device as described later. On the other hand, the trace control means 12 has a function of controlling the communication control interface 7 and the like and setting the trace information from the communication control device 9 in the trace information setting unit 13.

In addition, in this system, the trace information setting unit 13 or the like is used for R /
In addition to the trace information setting unit 13 for setting trace information such as W data and the number of times, and further trace information such as DMA trace information and I / O input / output information, CP
Address conversion means 14 for efficiently converting the trace information into an address signal for writing the trace information without using the U1, DMA3 or I / O address, and trace information under the address signal from the address conversion means 14. A RAM for storing, an IC card, and a trace memory 15 such as a hard disk are provided. Incidentally, these bus monitoring interface 11 and trace control means 12
The trace information setting unit 13 constitutes a bus monitoring means.

Next, the operation of the above system will be described. An example of tracing the memory data and the number of executions when input / output is performed at a specific address will be described here.

First, when condition setting data such as a memory address, memory data, and the number of executions is input from an external communication control device 9 or the like, the communication control interface 7 performs a transmission error check on the condition setting data, and then, it is necessary. The condition setting data is taken out and sent to the trace control means 12. Here, the trace control means 1
2 is set in the trace information setting unit 13 after converting the condition setting data from the communication control interface 7 into necessary trace information.

In the bus monitoring interface 11, when the trace information is set in the trace information setting unit 13, the address of the CPU 1 on the bus line and the input / output instruction data of the bus line 2 are monitored to trace the trace information setting unit. When the input / output instruction is executed at the same address as the address set in 13, the fact is sent to the address conversion means 14 via the trace information setting unit 13. Here, in the address conversion means 14, after converting the address set in the trace information setting unit 13 into a trace memory address, the trace information is written in the trace memory 15 by using this converted address, and further in the trace memory 15. "1" is added and the execution count data is saved.

On the other hand, when the external communication control unit 9 reads the trace information, the communication control unit 9 sends out the transmission data for data read including the address data. Here, when the communication control interface 7 receives the transmission data and passes it to the trace control means 12, the trace control means 12 reads the trace information from the trace memory 15 under the address, and the trace information is sent via the communication control interface 7. It is sent to the external communication control device 9 by data transmission.

Therefore, according to the method of the above embodiment, when the CPU 1 is down due to an abnormality, the trace control means 12 receives the data read transmission data including the address data from the external communication control device 9. It is possible to easily read necessary data from the trace memory 15, for example, input / output data and input / output count trace for the memory 4, input / output data and input / output count trace for I / O, and instruction execution trace. further,
Since the communication control device 9 does not pass through the CPU 1, the data from the DMA 2 can be easily traced using the bus line 2.

Next, FIG. 2 is a diagram showing a hardware configuration of a computer system to which another embodiment of the system of the present invention is applied. In this system, since the CPU 1 and the DMA 3 may occupy the bus line 2 when the fault occurs, the bus release interface 2 is forcibly released.
1 and bus release control means 22 are provided. That is, the bus release control means 22 sets the address set by the communication control device 9 and the address of the CPU 1 stored in the RAS section 23 when the CPU 1 cannot operate due to the watchdog timer error, the memory parity error, or the like. When comparing and these addresses match, CPU1 and D
The operation of MA3 is stopped and the bus line 2 is released. As a result, the communication control device 9 can access information such as the memories 4 and I / O connected to the bus line 2 via the bus release control means 22 and the bus monitoring interface 11.

In the bus release control means 22, the bus release interface 2 is based on the detection signal from the snuggle step detection unit for each instruction of the trace information setting unit 13.
It is possible to hold the CPU 1 via 1 so that the operation of the CPU 1 can be executed for each single step. Besides, the present invention can be variously modified and implemented without departing from the scope of the invention.

[0023]

As described above, the present invention has the following effects. In the invention of claim 1, C
Even when the PU is down, the information in the trace memory can be easily acquired from the external device.

Next, in claim 2, a CPU and a DMA
By releasing the occupation of the bus line by, it is possible to easily obtain the information of the device connected to the bus line from the external device.

[Brief description of drawings]

FIG. 1 is a hardware configuration diagram showing an embodiment of a computer system to which a bus line monitoring system according to the present invention is applied.

FIG. 2 is a hardware configuration diagram showing another embodiment of a computer system to which the bus line monitoring system according to the present invention is applied.

FIG. 3 is a hardware configuration diagram of a computer system to which a conventional method is applied.

[Explanation of symbols]

1 ... CPU, 2 ... Bus line, 3 ... DMA, 4 ... Memory, 7 ... Communication control interface, 9 ... Communication control device (external device), 11 ... Bus monitoring interface, 12 ...
Trace control means, 13 ... Trace information setting section, 14 ...
Address conversion means, 15 ... Trace memory, 21 ... Bus release interface, 22 ... Bus release control means.

Claims (2)

[Claims] 1. A DM for a bus line derived from a CPU.
In a computer system in which A and a communication control interface are connected, and an external device is connected to the communication control interface, at least the communication control interface, a bus monitoring unit, and a trace memory are connected to the bus line, and the operation of the CPU. At this time, the bus monitoring means sends CP information from the bus line to trace information from the external device.
When it is determined that the U data input / output instruction is executed, the data is written in the trace memory, and when the CPU is down, the external device is stored in the trace memory via the communication control interface and the bus monitoring means. The bus line monitoring method is characterized by reading the trace information that is present. 2. A bus release control means is added to claim 1,
The bus release control means, when the address set by the external device and the address of the CPU match, the CPU releases the CPU.
And the operation of the DMA is stopped to release the bus line, and information such as memory and I / O connected to the bus line can be accessed from the external device via the bus monitoring means. Bus line monitoring method.