JP2844361B2 - Error recovery processing method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding an error recovery processing method for continuing normal processing for an abnormality occurring in a processing device belonging to a system having a plurality of processing devices, all the processing devices are in an abnormal state. The purpose of the present invention is to provide a reliable error recovery processing method that can restart the system and continue normal processing even in the event of an error. A unit is provided for each of the processing devices, and an all-inactive state detection unit that determines whether all of the processing devices are in an inactive state, and an all inactive state detection unit that determines that all of the processing devices are in an inactive state. And a reset signal sending unit for sending a reset signal.

[Industrial applications]

The present invention relates to an error recovery processing method, and more particularly to an error recovery processing method for continuing normal processing for an error occurring in a processing device belonging to a system having a plurality of processing devices.

[Conventional technology]

 Conventionally, there has been a system as shown in FIG.

This system is composed of a plurality of processing units 6 (i); i = 1, 2,... (Computers), and each processing unit monitors each other for abnormalities. An abnormal recovery method has been used in which the remaining processing devices continue the operation of the system.

[Problems to be solved by the invention]

By the way, in the conventional error recovery method, when an error occurs in each processing device one after another and finally the remaining processing devices are exhausted, the system cannot continue the processing. Had.

On the other hand, in general, computer failures are mostly temporary failures, and there is an empirical fact that the computer can continue normal processing by restarting.

Accordingly, the present invention has been made to provide a reliable abnormality recovery processing method that can restart the system and continue normal processing even when all the processing apparatuses fall into an abnormal state. It is.

[Means for solving the problem]

In order to solve the above technical problem, as shown in FIG. 1, the present invention is applied to a processing apparatus 1 (i) belonging to a system having a plurality of processing apparatuses 1 (i), i = 1, 2 to n. In an abnormal processing method for continuing normal processing in response to the abnormalities, a sleep instruction generating unit 1 (i) a for setting the processing apparatus 1 (i) to a halt state due to the abnormality generated in the processing apparatus 1 (i) is provided in each of the processing apparatuses. An all-inactive-state detecting unit 2 for determining whether or not all the processing devices 1 (i) are in an inactive state, and a reset signal to all of the processing devices when it is determined that all of the processing devices are in an inactive state. And a reset signal transmitting unit 3 for transmitting.

[Action]

Each of the processing devices 1 (i), i = 1, 2 to n is provided with a pause instruction generator 1 (i) a; i = 1, 2, to n. Means that the processing apparatus is in a halt state.

Even if an abnormality occurs, as long as there is at least one processing device that operates normally, the system continues normal processing by the processing device.

However, when the all-hibernation-state detecting unit 2 detects that all the processing units have become abnormal and the halt instruction generating unit has entered the halt state, the system normally continues processing. The reset signal sending unit 3 is notified of the fact.

Then, the reset signal sending unit 3 that has received the notification sends a reset signal to all the processing devices.

This is based on the empirical fact that computer failures are almost always temporary failures, and normal processing may be continued by restarting.

〔Example〕

 Next, examples of the present invention will be described.

 FIG. 2 shows an overall view of the system according to the present embodiment.

This device is a processing device 11 (i) such as a plurality of CPUs; i = 1, 2,.
And a halt instruction generation unit 11 (i) a corresponding to the halt instruction generation unit 1 (i) a for bringing the processing device into a halt state due to an abnormality occurring in the processing device 11 (i).
Is provided in each processing apparatus.

Further, in the present system, each processing device is a subsystem independent of the respective processing devices, and hardware control of the main body necessary for operating each processing device, provision of a means of conversation with an operating system (OS), It monitors the operation status of the system and performs diagnosis and the like.

 FIG. 3 shows the monitoring device in detail.

The monitoring device is constituted by a CPU, a monitoring processing unit 21 corresponding to the all halt state detection unit 2 and the reset signal transmission unit 3, and a hardware / access unit for writing or reading access to a control register of each processing device. Access section 22
And a memory for storing a table corresponding to each processing device, which indicates whether or not each of the processing devices 11 (i); i = 1, 2, 3,... Is in a halt state (pause state). Control table 23,
It has a management unit 24 used to smoothly operate a system for processing and execution of input / output operations with an external storage device, execution order, error processing, and the like.

 The device according to the present embodiment operates as follows.

If it is determined that an abnormality has occurred in each of the processing units 11 (i); i = 1, 2,... And the processing unit cannot continue normal processing, the halt instruction generation unit 11 (i) ; i = 1,2,
Sets the processing apparatus in a halt state. The operating status of each processing device, that is, whether or not the processing device is in the halt state is displayed in the status register of each processing device 11 (i); i = 1, 2,.

As shown in the flow chart of FIG. 5, the monitoring device 20 determines in step SJ1 that the hard access unit 22
1 (i); a read (access) instruction is periodically issued to the status registers of i = 1, 2,. The read information, that is, information as to whether the apparatus is in the halt state or not is recorded in the control table 23 for each processing device as shown in the upper part of FIG.

In step SJ2, the monitoring processing unit 21 periodically accesses the control table 23, monitors the contents of the table, and determines whether all the processing devices are in the halt state.

If all the processing units 11 (i); i = 1, 2,... Are not in the halt state, the processing of the system is performed by the remaining processing units that are not in the halt state (even if there is only one). Is continued, and there is no instruction from the monitoring device.

On the other hand, as shown in the upper part of FIG.
When the monitoring processing unit 21 recognizes that all the processing devices are in the halt state in the table in (2), the process proceeds to step SJ3, and the hard access unit 22 causes the reset register of each processing device to: An instruction as shown in the middle part of FIG. 4 is given, and the hard access unit 22 writes a reset instruction signal to each processing device.

As a result, as shown in the lower part of FIG. 4, each processing device is started up, the processing is continued, and the table of the control table 23 reflects that the status register of each processing device is not in the halt state. The display has been made.

〔The invention's effect〕

As described above, according to the present invention, when an abnormality occurs in a plurality of processing apparatuses and normal processing cannot be continued, the processing apparatuses are set to a halt state, and the processing apparatuses are all in a halt state. When this is detected, a reset signal is sent to all the processing devices to start them up.

Therefore, it is possible to prevent a situation in which all the devices are in a halt state and the system is not operated at all, and a reliable system operation can be achieved.

[Brief description of the drawings]

1 is a block diagram showing the principle of the present invention, FIG. 2 is an overall block diagram according to an embodiment, FIG. 3 is a diagram showing a monitoring device according to the embodiment, and FIG. 4 is a functional description of the monitoring device according to the embodiment. FIG. 5, FIG. 5 is a processing flowchart of the monitoring apparatus according to the embodiment, and FIG. 6 is a block diagram according to the conventional example. 1 (i), 11 (i); i = 1, 2,... N Processing unit 1 (i) a (11 (i) a); i = 1, 2,. Holt command generator 2) (20) ... all pause state detector (monitor) 3 (20) ... reset signal transmitter (monitor)

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Claims (1)

(57) [Claims] 1. A plurality of processing units {1 (i), i = 1,2 to n}
An abnormal processing method for continuing normal processing with respect to an abnormality occurring in the processing device {1 (i)} belonging to the system having A sleep instruction generating unit {1 (i) a} for each of the processing units, and a sleep state detection unit (2) for determining whether all the processing units {1 (i)} are in a sleep state. A reset signal sending unit (3) for sending a reset signal to all of the processing devices when it is determined that all of the processing devices are in the idle state.