JPS63158650A - Information processor - Google Patents

Abstract

PURPOSE:To execute all data accesses by selecting a first memory interface bus as a bus for executing the data access when a signal showing that an abnormality is generated in a second memory interface bus is received. CONSTITUTION:While a processor 11 executes a program via the second memory interface bus 6, when the abnormality is generated in the bus 6, a bus abnormality detecting circuit 15 outputs a bus abnormality signal to a bus control circuit 12. In the circuit 12, a request permission signal transmitted to a second memory interface bus control circuit 14 is stopped to output the request permission signal to a first memory interface bus control circuit 13. Thereby, the circuit 13 is controlled so as to execute the memory request from the processor 11 via the first memory interface bus 5. In such a way, the bus 5 or 6 is selected according to the state of the bus and the data access is carried out by one of them, so that all the data accesses can be executed without a difficulty.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to an information processing apparatus that selects any one of a plurality of memory interface paths to perform various data accesses.

(Prior Art) Conventionally, this type of information processing device has a configuration in which an address space in a memory is divided into a plurality of parts, and a memory interface path is connected to each address space one by one.

Therefore, when accessing data to a certain address space, the address is output to a memory interface path that is connected to the address space. That is,
The addresses output to each memory interface path were separately specified.

(Problems to be Solved by the Invention) In the conventional information processing device described above, when a certain memory interface path becomes abnormal and becomes unusable,
It becomes impossible to execute data access between the address space connected to the memory interface path, and as a result, there is a risk that the entire information processing system will stop functioning.

The present invention has been made to solve these problems, and it is an object of the present invention to provide an information processing device that can execute all data accesses without any trouble even if an abnormality occurs in any memory interface path. purpose.

(Means for Solving the Problems) In order to achieve the above object, the information processing device of the present invention has the following features:
A first memory interface path to which a central processing unit, a main storage device, and a plurality of input/output control devices are connected, and a second memory interface path to which devices other than the plurality of input/output control devices are connected. and the central processing unit includes a processor, an abnormality detection means for detecting an abnormality in the second memory interface path, and decodes an address from the processor and decodes the first or second memory interface path as a path for data access. Select one of the two memory interface paths, input a signal from the abnormality detection means, and perform data access when receiving a signal indicating that an abnormality has occurred in the second memory interface path. and path control means for selecting the first memory interface path as the desired path.

(Example) Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an information processing apparatus according to this embodiment, and FIG. 2 is a block diagram of a central processing unit in the same apparatus.

In FIG. 1, 1 is a central processing unit, 2 is a main memory in which commands from the central processing unit 1 and various data are stored, 3 is an input/output device, and 4 is a main memory that controls the input/output device 3. This is an input/output control device that exchanges data with the storage device 2. A plurality of input/output devices 3 and input/output control devices 4 are installed.

5 is a first memory interface path, to which the central processing unit 1, main storage device 2, and each input/output control device 4 are connected. Further, 6 is a second memory interface path, to which the central processing unit 1 and the main storage device 2 are connected.

The central processing unit 1 includes a processor 1 as shown in FIG.
1, a path control circuit (path control means) 12, a first memory interface path control circuit 13, a second memory interface path control circuit 14, and a path abnormality detection circuit (abnormality detection means) 15. processor 1
1 takes out, decodes, and executes instructions. The path control circuit 12 decodes the address output from the processor 11 and transfers the memory request to the first memory interface path 5.
It is determined whether the output should be made to the first memory interface path 6, or to the second memory interface path 6.

When the path control circuit 12 specifies the first memory interface path 5 as a path for data access, the first memory interface path control circuit 13
Based on the memory request from the processor 11, the same path 5
A request for memory data is made to the main storage device 2 via.

On the other hand, when the path control circuit 12 specifies the second memory interface path 6 as a path to which data should be accessed, the second memory interface path control circuit 14 performs a process based on a memory request from the processor 11 via the second memory interface path 6. Then, a request for memory data is made to the main storage device 2.

The path abnormality detection circuit 15 monitors the state of the second memory interface path 6, and outputs a path abnormality signal to the path control circuit 12 when an abnormality such as no response in the path or a path parity check occurs.

When this path abnormality signal is input, the path control circuit 12 designates the first memory interface path 5 as the path to which data access is to be made, regardless of the determination based on the address output from the processor 11.

Next, the operation will be explained.

When the second memory interface path 6 is operating normally, memory requests from the processor 11 are executed via the second memory interface path 6 to which the input/output control device 4 is not connected. This is because if the input/output control device 4 uses the first memory interface path 5, if a memory request from the processor 11 is made through the same path 5, the execution will be delayed. Therefore, during normal operation, the first memory interface path 5 is used to transmit input/output commands to the processor 11 and the input/output control device 4, to read the status of the input/output control device 4, and from the input/output control device 4 to the main storage device 2. It is used for operations of the input/output control device 4, such as data transfer to the input/output control device 4.

Processor 11 is the second memory, interface path 6
If an abnormality occurs in the path 6 while the program is executed via the path 6, the path abnormality detection circuit 15 outputs a path abnormality signal to the path control circuit 12.

When the path control circuit 12 receives the path abnormality signal, it stops the request permission signal that is transmitted to the second memory interface path control circuit 14 during normal operation, and outputs the request permission signal to the first memory interface path control circuit 13. .

Thereby, the first memory interface path control circuit 13 controls the memory request from the processor 11 to be executed via the first memory interface path 5.

In this way, the first or second memory interface path 5 or 6 is selected depending on the status of those paths, and data access is executed using either path, so all data accesses are executed without any problems. can do.

(Effects of the Invention) As explained above, according to the information processing device of the present invention,
The first or second memory interface path is selected depending on the status of those paths, and data access is executed using either path, which has the effect of allowing all data accesses to be executed without any problems. .

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an information processing apparatus according to an embodiment of the present invention, and FIG. 2 is a block diagram of a central processing unit in the same apparatus. 1...Central processing unit 2...Main storage device 3...
Input/output device 4... Input/output control device 5... First memory interface path 6... Second memory interface path 11... Processor 12.
...Path control circuit 13...First memory interface path control circuit 14...Second memory interface path control circuit 15...Path abnormality detection circuit Figure 1 Figure 2

Claims (1)

[Claims] A first memory interface path to which a central processing unit, a main storage device, and a plurality of input/output control devices are connected, and a second memory interface path to which devices other than the plurality of input/output control devices are connected. and the central processing unit includes a processor, an abnormality detection means for detecting an abnormality in the second memory interface path, and decodes an address from the processor and decodes the first or second memory interface path as a path for data access. Select one of the two memory interface paths, input a signal from the abnormality detection means, and perform data access when receiving a signal indicating that an abnormality has occurred in the second memory interface path. An information processing apparatus comprising: path control means for selecting the first memory interface path as the desired path.