JPS6041145A - Disc cache device - Google Patents

Abstract

PURPOSE:To process simultaneously accesses from plural CPUs by dividing data transfer from a connection port in accordance with priority and executing the transferred data when the titled device is simultaneously accessed from the connected plural CPUs. CONSTITUTION:When a CPU1 sets up a logical connection request line CNRQ1, a microprocessor 47 in a controller 20A is interrupted and a CPU1 processing task receives a command from the CPU1. When the received command is a read instruction, the task searches a directory 23 and checks whether necessary data exist or not in a cache memory 21. If data exist in the memory 21, the address of the memory 21 and the number of data are set up in a DMA controller 50 and a transfer request signal from the CPU1 is inputted to a transfer request line DREQ1 of the controller 50. If data transfer to CPUs 2, 3 is not executed, the controller 50 reads out immediately data from the cache memory 21, and transfers the read-out data to the CPU1, and when data transfer to the CPUs 2, 3 is under operation, the transfer should be started after ending the transfer of one byte.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a disk cache device, and particularly to a disk cache device that connects a plurality of central processing units and can be accessed simultaneously from the plurality of connected central processing units. Regarding equipment.

[Background of the invention]

Generally, when configuring a multi-system in which one magnetic disk device is shared by a plurality of central processing units, the following mechanism is adopted.

When a logical connection is made between the magnetic disk device and a plurality of central processing units, a connection request made from the central processing unit to the magnetic disk device is scanned, and the central processing unit that received the connection request is scanned. A switching mechanism is required to select a processing device and logically connect the magnetic disk device and the central processing unit. When a disk cache device is applied to a multi-system employing this switching mechanism, the configuration shown in FIG. 1 or 2 will be obtained.

FIG. 1 is a configuration diagram showing an embodiment in which there is only one disk cache device. In FIG. 1, central processing units (CPUs) 1 to 3 that process data and one magnetic disk device 6 shared by the central processing units 1 to 3 are connected to each other by a switching mechanism (MAC) 4. ~3 is connected. At this time, a disk cache device that serves as a high-speed buffer for the storage data of the magnetic disk device 6 is provided between the magnetic disk control device 5 that controls the operation of the magnetic disk device 6 and the switching mechanism 4. 7 is provided.

In the above configuration, the central processing units 1 to 3, the disk cache device 7, the disk control device 5, and the magnetic disk device 6 are logically connected by a switching mechanism 4. and the disk cache device 7,
Alternatively, when the disk control device 5 is executing an instruction from any one of the central processing units 1 to 3, it is necessary to maintain the logical connection until a series of operations within the magnetic disk device 6 is completed. During this time, access from the central processing units 1 to 3 of other systems is made to wait by the switching mechanism 4.

Generally, the waiting time is several tens of milliseconds for head movement, several milliseconds for waiting for rotation, and a data transfer time corresponding to the number of transferred words.

FIG. 2 is a block diagram showing an embodiment in which the disk canon device is of several sizes. In FIG. 2, the same components as in FIG. 1 are designated by the same reference numerals, and their explanations will be omitted. The difference between this embodiment and FIG. 1 is that the connection positions of the switching mechanism 4 and the disk cache device 7A are switched. However, there is Vc. The seven disk cache devices are individually provided for the central processing units 1 to 3, and the groups of disk cache devices 7A are connected to each other by a communication mechanism 8.

In the configuration, the disk cache device 7A has the following features:
It is installed for each of the central processing units 1 to 3, and one of the central processing units 1 to 3 has the disk cache device 71°C,
or the disk city IJ control device 5 and the disk device 6
Even if one central processing unit is accessing the disk cache device 7A, the other central processing units 1 to 3 can access the disk cache device 7A.

This is possible if the disk cache device 7A is connected to each of the central processing units 1 to 3 (in other words, it can always operate for the connected central processing units 1 to 3). 75) The disk cache device 7A
When there is no data in the magnetic disk device 6 and the magnetic disk drive 6 must be accessed, the switching mechanism 4 waits as in the embodiment shown in FIG.

Furthermore, in this embodiment, the following method is used as a means for maintaining the continuity of data on each disk cache device 7A. That is, the central processing unit 1
When the data A stored in a certain area on the magnetic disk device 6 is rewritten to A', this data A is transferred to the disk cache device 7 connected to the central processing unit 2.
Suppose that it is stored in A. At this time, when the central processing unit 2 accesses the area A on the disk cache device 7A, the data becomes the old data A, not the data A' rewritten by the central processing unit 1. To prevent this from happening,
When data on the magnetic disk device 6 is rewritten, a communication mechanism 8 is provided that notifies the other disk cache devices 7A of which area's data has been rewritten.

Therefore, the disk cache device 7A invalidates the data A, and when the central processing unit 2 accesses this area next, the magnetic disk device 6 stores the data A.
′, data continuity can be maintained. However, due to processing that maintains the continuity of one data,
The number of heads of the disk cache device 7A increases.

FIG. 3 is a block diagram showing the configuration of the disk cache device shown in FIG. 2. In FIG. 3, the disk cache device 7A has a controller 20 that controls the entire disk cache device 7A, and a cache memory 21 in which data on the magnetic disk device 6 is stored by an address node 42. Connected. It is connected to the controller 20 by a command register 22 in which commands from the central processing units fx~3 are stored, and address buses 40 and 411f.
There is a directory 23 in which the source and current addresses of data stored in the cache memory 21 are stored. Further, as a mechanism for connecting the disk cache device 7A to other devices, data buses 30 and 31 for transferring data are connected to the central processing units 1 to 3 via gates 33. As for control relations, a control line 34, a C1'JRQ'i line 35 whose logical connection is requested from the central processing units 1 to 3, and a response line CNAKO line 36 for the CNR and QI lines 35 are connected. Also,
A data bus 3 that transfers data to the switching mechanism 4
0 and 32 are connected through gate 33.

Regarding control, there is a control line 37, and a CNRQO line 38 that requests logical connection from the disk cache device 7.
and a response line CNAKI line 3 for the CNRQO line 38.
9 is connected. Next, for the other device disk cache device 7A, the other device disk cache device 7A
A write request line WREQ043 to the disk cache device 7A, a write request line WREQI4 from the other disk cache device 7A
4 and a communication line WAD box 45 for notifying the fixed address on the magnetic disk device 6 are connected via the gate 33.

An outline of the operation in the above configuration will be explained with reference to FIGS. 4(a), (b), and (C).

FIG. 4 is a flowchart illustrating the operation of FIG. 3. In FIG. 4, in step 100, the central processing units 1 to 3, before accessing the disk cache device 7i or the magnetic disk device 6,
CNRQI 35 f m is set to "1°'" and logical connection is established. On the other hand, the disk cache device 7
A constantly monitors the CNRQI35. The CNR
When QI 35 is set to 1”, step 110
(Set the CNAKO36 to 1" from fi, and
＋The power of 2t logical connections to the processing devices 1 to 3.
ill be known.

Then, in step 120, commands from the central processing units 1 to 3 are received and stored in the command register 22, and in step 130, it is determined whether the command is a lead branch. Command 75: In the case of an IJ-do command, the directory address pointer is incremented one by one from the first address of the directory IJ 23 in step 140, and the j-row directories are searched. Here, it is determined whether the data accessed from the central processing units 1 to 3 is on the disk cache device 7A (7)-step 150. This judgment is based on the data (
The determination is made based on whether the accessed data is included in the track address obtained through the bus 41. Next, when the data accessed from the central processing units 1 to 3 exists on the disk cache device 7A, the data is stored in the central processing units 1 to 3 through the cache memory 21 and the data node 31 in step 160. 3
data is transferred to. When the data transfer is completed, a completion report is sent to the central processing units 1 to 3 in step 170. Further, step 180 determines that the CNR
Monitor that QI35 is set to 0'' and check that the CNR
If QI35 becomes 0'', proceed to step 190, and the corresponding CN
The AKO 36 is reset and the process returns to step 100.

On the other hand, if the command is a write command in step 130, or if the necessary data does not exist in the cache memory 21 in step 150, in step 200, the logical connection with the disk controller 5 is established. The CNRQO3B is set so that At this time, if the magnetic disk device 6 can be used, the switching mechanism 4 sets the CNAKI 39 to 1", so in step 210 the CNAKI 39 is set to 1".
J9 is monitored, and when the CNAKI 39 is set, the command is transferred to the magnetic disk device 6 in step 220. Then, in step 230, read by the command stored in the command register 22,
Or a write operation is executed. Here, if the command is a write command, WREQ043 is set, and the other disk cache devices 7A are notified that the write command has been executed, and the WAD
The write address is communicated by R45. In the disk cache device 7A that received the notification, if the corresponding data exists on the cache memory 1) 21, it is invalidated. Further, notifications from other disk cache devices 7A are made by the W EQI 44. Next, when the read/write operation is completed, a process for terminating the operation on the magnetic disk device 6 side is executed in step 240, and then the CN box Q038 is reset in step 250.

After executing the end processing of the operation on the central processing units 1 to 3 in step 260, in step 270 the CPU
After confirming that the NRQI 35 becomes 0'', the CNAKOa 6 is reset in step 280, and the process returns to step 100.

Therefore, in the embodiment shown in FIG. 1, there is only one disk cache device, and there is no need for communication between the disk cache devices as in the embodiment of FIG. 2, and the configuration of the disk cache device is Although it is simpler, it is not possible to simultaneously process accesses from the central processing unit.

On the other hand, in the embodiment shown in FIG. 2, although it is possible to simultaneously process accesses from the central processing unit, the amount of hardware and overhead increases due to the need for interconnection between disk cache devices. There was a drawback.

[Purpose of the invention]

An object of the present invention is to eliminate the drawbacks of the prior art, and to enable access to a disk cache device from another central processing unit even when one central processing unit is accessing a magnetic disk device or a disk cache device. It is an object of the present invention to provide a disk cache device that can improve the throughput of the entire system.

[Summary of the invention]

In order to achieve the above object, the present invention provides a connection port for connecting a plurality of central processing units at the same time to a disk cache device, and when access requests are made simultaneously from the plurality of connected central processing units, a predetermined access request is made. The invention is characterized in that accesses from a plurality of central processing units can be processed simultaneously by processing data according to the priority order and dividing and executing data transfer from the connection port according to the priority order. .

[Embodiments of the invention]

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 5 is a configuration diagram showing an embodiment of a disk cache device to which the present invention is applied. In FIG. 5, the same components as those in FIG. 1 are given the same reference numerals, and their explanations will be omitted. This embodiment differs from FIG. 1 in that a disk cache device 7B is provided between the central processing units 1 to 3, the magnetic disk control device 5, and the magnetic disk device 6 without providing the switching mechanism 4. It is at the point that I have set. and,
The disk cache device 7B has connection ports to which three central processing units can be connected, and the data length when accessing the magnetic disk device 6 is one track length (
(12 kilobytes) is fixed.

FIG. 6 is a block diagram showing one embodiment of the configuration of the disk cache device shown in FIG. 5. In FIG. 6, the same components as those in FIG. 3 are given the same reference numerals, and their explanations will be omitted. This embodiment differs from FIG. 3 in that the communication mechanism 8 to the other disk cache device 7A is eliminated, and two sets of connection ports for the central processing units 1 to 3 are added.

In the above configuration, the disk cache device 7B has the following features:
Except for the controller 2OA that controls the entire disk cache device 7B and the command register 22A expanded to be able to store commands from the three central processing units 1 to 3 at the same time, there is no difference from the embodiment shown in FIG. There are no major changes. Further, the connection port between the central processing units 1 to 3 and the disk cache device 7B is connected to the central processing unit 1 to be connected.
.about.3, but the contents of the signals are the same as in the embodiment shown in FIG.

FIG. 7 is a block diagram showing one embodiment of the configuration of the controller shown in FIG. 6. In FIG. 7, a microprocessor (
An MPU 47, a ROM 48 in which a program defining the operation of the microprocessor 47 is stored, and a RAM 49 for operating conditions are connected. A control circuit 51 that controls the microprocessor 47 and interfaces with the central processing units 1 to 3 and the magnetic disk device 6 is connected to the microprocessor 47 through various information buses. Furthermore, data transfer between the interrupt controller 52 that generates interrupts to the microprocessor 47, the central processing units 1 to 3, the magnetic disk device 6, and the cache memory 21 is performed via the microprocessor 47 by CNELQ1-3. without any
An independently executing DMA controller 50 is connected to the p1 microprocessor 47 by various information buses.

Next, multiplexer<MUX) 53 and demultiplexer (DMUX 1154) are connected to configure the controller 20A.

In the above configuration, a 1-byte data transfer is executed by first setting a transfer confirmation signal EQO 55 by the transfer request source and then returning a transfer confirmation signal ACKI 56 in response. Here, the multiplexer 53 selectively inputs only the signal of the central processing unit 1 to 3 currently accessing the magnetic disk device 6 from among the transfer request signals from the central processing units 1 to 3. 8 manual effort) and output it to the magnetic disk device 6. At this time, the transfer request signal from the central processing units 1 to 3 is transmitted to the DM.
For the purpose of synchronizing with the A controller, it is input to the multiplexer 53 as an OR condition with the DACK signal. Further, the demultiplexer 54 determines which central processing unit 1 to 3 is the response to the transfer request from the ACKI 56 from the magnetic disk device 6 based on the select input, and sends it to the bDMA controller 50.
Execute data transfer. Note that the transfer requests DREQ 0 to 3 to the DMA controller 50 are transferred between the central processing units 1 to 3 and the cache memory IJ 21, so the transfer requests DREQ. The transfer request signals from the central processing units 1 to 3 are set as an OR condition. - FIG. 8 is a block diagram showing an example of the program structure of a microprocessor. 8th
In the figure, at 08300, hardware management and task management of the disk cache device 7B are processed;
CP on which commands from the central processing units 1 to 3 are processed
It is composed of U1-3 processing tasks 310-330, and an idle task 340 that is processed when none of the central processing units 1-3 is activated.

Here, since the operations of the processing tasks for each central processing unit are the same, nine operations will be explained using the CPU≠1 processing task 310 as an example.

FIG. 9 is a flowchart illustrating the operation of the CPU'U processing task shown in FIG. In FIG. 9, when the central processing unit 1 sets CNRQl, an interrupt is input to the microprocessor 47, which causes the 08300 to
The PUsl processing task 310 is activated. The CPU+1
Processing task 310 includes, in step 400, CNA
KOl is set and a command is received from the central processing unit l according to step 410. Next, step 4
20, it is determined whether or not it is a read command. If it is a read command, the directory 23 is searched in step 430, and it is determined in step 440 whether the necessary data exists on the cache memory 21.

If there is data to be stored in the cache memory 21, a citator transfer is performed in step 450. The data transfer at this time is between the central processing unit 1 and the cache memory 21, and the transfer procedure is as follows.
The address of the cache memory 21 and the number of data to be transferred are set in the DMA controller 50, and a transfer request signal from the central processing unit 1 is sent to the DMA controller 2.
input to DREQ1. At this time, DM
The A controller 50 immediately returns DACKl to the central processing unit 1 if data has not been transferred with the other central processing units 2 to 3, and also transfers the data to the cache memory 21.
The specified address data is read from the CPU 1 and transferred to the central processing unit 1. When data transfer with the other central processing units 2 to 3 has already been executed, K waits until the 1-byte data transfer is completed before data transfer with the central processing unit I is executed.

In this way, when the specified amount of data transfer is completed, the block 460 reports the completion to the central processing unit 1 and waits until f*CNRQ1 is reset in step 470. Thereafter, in step 480, CNAKO1 is reset and the process ends. In step 420, if the command is a write command, or if the required data does not exist in the cache memory 21 in step 440,
In step 490, it is determined whether the other central processing units 2 or 3 are currently using the magnetic disk device 6. If the other central processing units 2 to 3 rarely use the magnetic disk device 6, step 570
Wait until the space device 6 becomes vacant, and then perform C by step 500.
NRQO is set to ensure logical connection with the magnetic disk device 6.

When the other central processing units 2 to 3 are not using the magnetic disk device 6, CNRQO is set immediately.

Next, in step 510, the process waits until CNAKI is set, in step 520, a command is transferred to the magnetic disk device 6, and in step 530, a cache operation according to the data read/write is executed. Data transfer here is executed between the central processing units 1 to 3 and the magnetic disk devices 60 via the disk storage device 7B. At this time, the transfer request signal from the central processing unit 1 is sent to the magnetic disk device 6, and the ACKII signal from the magnetic disk device 6 is connected to the DREQ input of the DMA controller 50. Furthermore, the REQO signal is an OR condition of the 1) ACK signal of the DMA controller 50 and the transfer request signal from the central processing unit 1, and during data transfer, the DM
It is designed to be synchronized with both the A control unit 50 and the central processing unit 1. Note that when a write command is executed, both the cache memory 21 and the magnetic disk device are read, and when a read command is executed, it is possible to write to the character memory and the central processing unit 1
will be forwarded to. In this way, when the data transfer is completed, in step 540, processing for terminating the operation on the magnetic disk device side is executed, and in step 550, the CNRQ
After resetting, the processing for terminating the operation on the central processing unit l side is executed in step 560, and step 470
Return to

That is, according to the above example, even while one central processing unit is accessing the cache memory or the magnetic disk drive, other central processing units can access the cache memory. , multiple central processing units can transfer data simultaneously, which has the effect of improving the throughput of the entire system.

In the non-example, three central processing units were used, but by increasing the number of connection ports and the number of channels of the DMA controller, it is possible to connect to a larger number of central processing units.

〔Effect of the invention〕

As can be easily understood from the above description, the present invention provides a disk cache device with a connection port for connecting a plurality of central processing units at the same time, and allows access requests to be made simultaneously from the plurality of connected central processing units. In such cases, data transfer is divided and executed according to a predetermined priority order, so accesses from multiple central processing units can be processed simultaneously, which has the advantage of improving the throughput of the entire system.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment when there is one disk cache device, FIG. 2 is a configuration diagram showing an embodiment when there are multiple disk cache devices, and FIG. A block diagram showing the configuration of the disk cache device shown in the figure,
Figure 4 is a flowchart explaining the operation of Figure 3;
6 is a block diagram showing an example of the configuration of the disk cache device shown in FIG. 5, and FIG. 7 is a block diagram showing an example of the configuration of the disk cache device shown in FIG. 8 is a block diagram showing an example of the configuration of the controller shown in FIG. 8. FIG. 9 is a block diagram showing an example of the program configuration of the microprocessor.
70-Chart illustrating the entire operation of the U processing task. DESCRIPTION OF SYMBOLS 1-3...Central processing unit, 4...Switching mechanism, 5-Magnetic disk control device, 6...Magnetic disk device, 7°7A, 7B...Disk cache device, 8...Communication mechanism , 20.2OA...controller, 21...
Cache memo IJ, 22, 22A... Command register, 23... Directory. Agent Patent attorney Akio Takahashi flc Shizuka 4 sides and θ) Shell 4fJ Tonji Kootogu

Claims (1)

[Claims] 1. In a disk cache device that is located between a central processing unit that processes data and a magnetic disk device that stores data used by the central processing unit and serves as a high-speed buffer for data stored in the magnetic disk device, the A disk cache device is provided with a connection port for simultaneously connecting a plurality of central processing units, and a means for time-sharing processing of data transfer with the plurality of connected central processing units is provided. f: A disk cache device that is configured to be accessible.