JPS633358A - Multiprocessor - Google Patents

Abstract

PURPOSE:To quickly deliver a processing request by providing a pair of microprocessors to write data to a shared memory with an interruption request and then read the data out of the shared memory after discontinuation of working when an interruption is received, a pair of interruption generating circuits, etc., for the formation of a multiprocessor. CONSTITUTION:The interruption controllers 15 and 16 are added to a normal multiprocessor together with the interruption generating circuits 17 and 18. The circuits 17 and 18 are connected to the corresponding microprocessors 1 and 2, address buses 5 and 8, and control buses 6 and 9 respectively. While the controllers 15 and 16 are connected to the corresponding processors 1 and 2, data buses 4 and 7, the buses 5 and 8, and the buses 6 and 9 respectively. When an interruption signal is instructed from the processor 1 via the bus 6, an interruption request signal S3 is sent to the controller 16 from the circuit 18 has the same action and sends an interruption request signal S6 to the controller 15.

Description

Detailed Description of the Invention [Object of the Invention] (Industrial Application Field) The present invention relates to a multiprocessor having a pair of microprocessors and a shared memory, and particularly relates to a multiprocessor having a pair of microprocessors and a shared memory. It performs interrupt processing when sending.

(Prior Art) A conventional multiprocessor having a pair of microprocessors and a shared memory is shown in FIG. 4, for example. As shown in the figure, in this multiprocessor, a microprocessor 1 is connected to a shared memory 3 via a data bus 4, an address bus 5, and a control bus 6, and a microprocessor 2 is connected to a shared memory 3 via a data bus 7,
They are connected via an address bus 8 and a control bus 9. Shared memory 3 can be accessed simultaneously by two microprocessors 1.2, and access permission control signals S1 and S2 are sent from shared memory 3 to microprocessors 1.2, respectively. This access permission control signal S1
, S2, the memory read and write operations of the microprocessor 1.2 are executed or made to wait for some time.

- Generally, in the case of a general-purpose microprocessor, the access permission control signals S1, S2 are called ready signals or wait signals. The shared memory 3 also has an arbitration function that gives priority to one of the microprocessors even if the memory is accessed by two microprocessors 1.2 at the same time.

Next, the operation of this multiprocessor will be explained. When transmitting information from microprocessor 1 to 2 via shared memory 3, microprocessor 1 first sends information via data bus 4,
Using address bus 5 and control bus 6,
Write information to shared memory 3. The other microprocessor 2 operates in the same manner as the data bus 7 and the address bus 8.
and reads information from the shared memory 3 via the control bus 9. Information can also be transmitted from the microprocessor 2 to the microprocessor 1 in the same way.

FIG. 5 shows the shared memory 3 when one microprocessor 1 requests processing from the other microprocessor 2.
This is the data map within. As shown in the figure, the shared memory 3 consists of n bytes.

The content of processing for each byte is determined in advance in correspondence with the byte number. The first bit 13 indicates whether or not a process corresponding to the byte number is requested; for example, if the bit is "1", it indicates that a process is requested;
“O” indicates that there is no processing request. In the case of FIG. 5, the process corresponding to byte number O has issued a request. Furthermore, the area 14 is a place where data necessary for the processing is transferred. , nothing is written if no data is needed.

In addition, the range of predetermined byte numbers is the content that microprocessor 1 requests microprocessor 2 to process, and the range of other predetermined byte numbers is the content that microprocessor 2 requests microprocessor 1 to process. Each contains the content that requests processing.

(Problems to be Solved by the Invention) As described above, in the conventional multiprocessor, one microprocessor 1 (or 2) issues a processing request to the other microprocessor 2 (or 1) via the shared memory 3.
If there is an urgency to the process, there is a problem in that it is not possible to promptly notify the other party of this.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiprocessor capable of quickly transmitting a processing request from one microprocessor to another microprocessor in order to solve the above-mentioned problems.

[Structure of the Invention [Means for Solving the Problems] To achieve the above object, the present invention includes a shared memory, which is connected to the shared memory, writes data to the shared memory when an interrupt request is made, a pair of microprocessors that stop the current operation and read data from the shared memory when receiving an interrupt signal; a pair of interrupt generating circuits that generate an interrupt request signal; and a pair of interrupt generating circuits that are provided corresponding to the pair of microprocessors and generate the interrupt signal to the corresponding microprocessor upon receiving the interrupt request signal. It is characterized by comprising an interrupt control circuit.

(Operation) When one microprocessor issues an interrupt request, this interrupt request is input to the interrupt generation circuit corresponding to this microprocessor, and this interrupt generation circuit generates an interrupt request signal. At the same time, this microprocessor writes predetermined data to the shared memory. The interrupt request signal is input to the interrupt control circuit corresponding to the other microprocessor, and the interrupt signal is input from this interrupt control circuit to the microprocessor corresponding to this interrupt control circuit. When the microprocessor receives this interrupt signal, it stops its current operation and reads the data written to the shared memory.

By issuing an interrupt request in this way, it is possible to stop the operation of the other microprocessor even if it is in operation, and to quickly send data from one microprocessor to the other microprocessor.

(Example) An example of the present invention will be described in detail below based on the drawings. FIG. 1 is a configuration block diagram of a multiprocessor according to this embodiment, and elements that perform the same functions as those of the conventional multiprocessor shown in FIG. 4 are given the same numbers and redundant explanations will be omitted. In this embodiment, a conventional multiprocessor includes an interrupt controller 15, 16 and an interrupt generation circuit 1.
7.19 has been added.

Interrupt generation circuits 17.18 are connected to respective microprocessors 1.2 by address buses 5.8 and control buses 6.9.

Interrupt controllers 15 and 16 each have a corresponding microprocessor 1.2, data bus 4.7, and address bus 5.
．． 8, connected via control bus 6.9.

When the interrupt generation circuit 17 receives an interrupt request instruction from the microprocessor 1 via the control bus 6, it sends an interrupt request signal S3 to the interrupt controller 16. The interrupt generation circuit 18 similarly operates to send an interrupt request signal S4.

Upon receiving the interrupt request signal S3, the interrupt controller 16 sends an interrupt signal S5 to the microprocessor 2. The interrupt controller 15 similarly performs the operation of sending the interrupt signal S6.

Next, the operation of this embodiment will be explained based on the flowcharts of FIGS. 2 and 3, taking as an example the case where the microprocessor 1 requests a certain process to the microprocessor 2.

First, the microprocessor 1 processes the data (
5) is written into the shared memory 3 (step 201). Next, the interrupt signal generation circuit 17 is accessed to generate the interrupt request signal S3.
is sent to the interrupt controller 16 of the microprocessor 2,
The interrupt controller 16 sends an interrupt signal S5 to the microprocessor 2 (step 202). microprocessor 2
When controlling the control bus 9 to respond to the interrupt (step 301), the interrupt controller 16 transmits the interrupt processing vector address corresponding to the interrupt level of the interrupt request signal via the data bus 7. microprocessor 2
tell to. The microprocessor 2 executes an interrupt processing routine based on the above vector. In the interrupt processing routine, data written by the microprocessor 1 is read from a location in the shared memory 3 predetermined for the processing routine (step 302), and necessary processing is performed (step 303).

In this way, in this embodiment, when data is sent to one microprocessor or the other microprocessor, interrupt processing is performed for the other microphone C processor, so processing can be quickly transmitted and processed. .

[Effects of the Invention] As described in detail above, according to the present invention, processing requests can be quickly transmitted from one microprocessor to the other microprocessor.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the configuration of a multiprocessor according to an embodiment of the present invention, FIGS. 2 and 3 are flowcharts showing the operation of this multiprocessor, FIG. 4 is a block diagram of the configuration of a conventional multiprocessor, and FIG. 5 is a block diagram of the configuration of a conventional multiprocessor. This is a memory map of shared memory in a conventional example. 1.2...Microprocessor, 3...Shared memory,
15.16...Interrupt controller, 1718...Interrupt generation circuit.

Claims (1)

[Scope of Claims] A shared memory, which is connected to the shared memory, writes data to the shared memory when an interrupt request is made, and stops the current operation and reads data from the shared memory when receiving an interrupt signal. a pair of microprocessors; a pair of interrupt generation circuits provided corresponding to the pair of microprocessors and generating an interrupt request signal from one microprocessor to the other microprocessor; 1. A multiprocessor comprising: a pair of interrupt control circuits provided corresponding to the microprocessors, and generating the interrupt signal to the corresponding microprocessor upon receiving the interrupt request signal.