JPS5920067A - Memory system - Google Patents

Abstract

PURPOSE:To attain easily the execution at rising, by providing a memory bus RAM/ROM switching control line and executing a prescribed specific program with an ROM and a usual changing program with an RAM. CONSTITUTION:The RAM2 and the ROM3 are connected to a CPU1 via a memory bus 10. The bus 10 consists of a data line 11, a memory address line 12 and a control line 13. The line 13 includes an RAM/ROM switching control line 14 to give an RAM/ROM switching control signal to the RAM2 and the ROM3. Thus, the RAM2 and the ROM3 are used distinctively with the RAM/ROM switching control signal when the RAM2 and the ROM3 are set for memory addresse 0-4k addresses, in taking the memory capacity of the RAM2 and the ROM3 as 4k-word.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a memory system, and more particularly to a RAM based on memory addresses supplied to a memory bus.

The present invention relates to a memory system that accesses ROM.

[Prior art]

Traditional memory systems include a central processing unit that provides access control signals and memory addresses and sends and receives data;
a memory path consisting of a control line that transfers the access control signal, a memory address line that transfers the memory address, and a data line that transfers the data; and when the memory address is included, the access control signal and the memory a ROM memory that accesses the data based on an address; and a RAM that accesses the data based on the access control signal and the memory address when the memory address is included.
It consists of memory.

In other words, in the conventional memory path system, for example, if the memory capacity of both RAM memory and ROM memory is 4, then R
The memory address area of AM memory is O at the memory address.
If the address is set to 4 to 4, the address area of the ROM memory will be set as the consecutive memory addresses from 4 to 8, and the memory address will be set to RAM memory or ROM.
Memory was used to distinguish between.

In this way, conventional memory systems use R on the memory bus.
When connecting AM and ROM, the memory address is 几A.
M, ROM had different consecutive addresses.

Therefore, when starting up a computer, if you want to start from a specific memory address and execute a predetermined job, usually a JOB program, the program is stored in the RAM from another location using some method, and then executed. There was a drawback that it had to be done.

That is, the conventional memory system has the disadvantage that it is not easy to execute at startup.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory system that can be easily implemented at startup.

That is, the purpose of the present invention is to
Having a switching control line eliminates the above drawbacks and makes it possible to connect either RAM memory or ROM memory at the same memory address, so that certain programs can be stored in ROM memory from the beginning, such as when starting up a computer. The purpose is to provide a memory bus that allows the contents of the ROM to be written and executed, and a normal changing JOB program to be executed with the program stored in the FtAM memory.

[Structure of the invention]

The memory system of the present invention has It AM/, [
(A central processing unit that supplies access control signals including OM switching signals and memory addresses and transmits and receives data, and a RAM that transfers the RAM/ROM switching control signal.)
A control line including the /ROM switching control line and transferring the access control signal, a memory bus extending from the memory address line transferring the memory address and the data line transferring the data, and the RAM/ROM switching control line. a ROM that accesses the data based on the access control signal and the memory address when a signal indicates
111. That is, the memory system of the present invention includes a memory and a RAM memory that accesses the data based on the access control signal and the memory address when the RAM/ROM switching control signal indicates. is configured to include a memory bus having a RAM/ROM switching control line.

That is, the memory system of the present invention includes a memory bus that has a RAM/ROM switching control line in the memory bus so that it is possible to switch and connect the FT, AM memory area, and ROM memory area at the same memory address. be done.

[Explanation of Examples]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

A RAM memory 2 and a ROM memory 3 are connected to the central processing unit R1 via a memory bus 10. The memory bus 10 includes a data line 11, a memory address line 12, and a control line 13.
It is made up of. In the control line 13, RAM/RO
Transfer the M switching control signal to the AM memory 2. A RAM/ROM switching control line 14 for supplying to the ROM memory 3 is included.

Therefore, for example, if both RAM memory 2 and ROM memory 3 have a memory capacity of 4 words, RAM memory 2 also has a memory capacity of 4 words.
Even if the OM memory 3 is set to addresses 10 to 4, it can be distinguished and used by the RAM/ROM switching control signal.

〔Effect of the invention〕

The memory system of the present invention has a ROM/A in the memory bus.
By adding an M switching control line, it is possible to instruct whether to access ROM or RAM, and since the same address can be assigned to ROM and RAM, programs etc. that will eventually be stored in ROM can be transferred to RAM at startup. In other words, by having the RAM/ROM switching control line in the memory bus, the memory system of the present invention has the effect of facilitating execution at startup.
RAM memory and ROM with the same memory address
This has the effect of allowing memory to be connected.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 1°°°°°°Central processing unit, 2...RAM memo 1c 3...ROM memo 1, 1, 10...
・・・Memory bus, 11・P・・・Data line, 12...
...Memory address line, 13°°゛...Control line,
14...RAM/ROM switching control line. Figure 1

Claims (1)

[Claims] A central processing unit that supplies an access control signal including a RAM/ROM switching signal and a memory address to transmit and receive data, and a RAM/ROM switching control line for transferring the RAM/ROM switching control signal and transmitting the access control signal. A memory path consisting of a control line to transfer, a memory address line to transfer the memory address, and a data line to transfer the data; a ROM memory that accesses the data based on the RAM/ROM switching control signal; and an RA that accesses the data based on the access control signal and the memory address when the RAM/ROM switching control signal indicates
A memory system comprising: M memory.