JPS62274452A - Dual port memory - Google Patents

Abstract

PURPOSE:To improve the data processing efficiency of a multiprocessor system by allowing only a desired microprocessor out of plural microprocessors sharing a system bus to perform the interrupt processing and holding the control operation in microprocessors which do not require the interrupt processing. CONSTITUTION:It is discriminated whether the interrupt request from microprocessor Mpu10-Mpu1i (Mpu20-Mpu2i) sharing one system bus SB1 (SB2) to microprocessor Mpu20-Mpu2i (Mpu10-Mpu1i) sharing the other system but SB2 (SB1) is permitted or not by a logic circuit LOG1 (LOG2) on a basis of data stored in an interrupt permission register RIM1 (RIM1), and interrupt signal phiirq20-phiirq2i (phiirq10-phiirq1i) are individually supplied to microprocessors Mpu20-Mpu2i (Mpu10-Mpu1i). Consequently, microprocessors which do not require the interrupt processing can continue the control operation as they are.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a dual-port memory, in which a plurality of microprocessors are connected to each port via a system bus, for example. The present invention relates to techniques that are effective when applied to multiprocessor systems.

[Prior art]

To improve the data processing capacity of the micro processor system l-, please refer to the "
As described in "Microcomputer Handbook" P679, it is possible to employ a multiprocessor system in which two processors share a dual port memory so that they can mutually access the memory individually.

The present inventors considered increasing the functionality of the entire system by connecting a plurality of microprocessors to each system bus connected to each port of such a dual port memory. In that case, in order to enable interrupts from each of the two ports of the dual port memory to the other port, an interrupt control circuit capable of outputting one type of interrupt signal each corresponding to both ports 1- is installed in the dual port memory. We considered establishing a That is, when an interrupt request is issued from the processor on one port side to the processor on the other port side, and the request is accepted.

From the other port side, the same interrupt signal is provided to all microprocessors coupled to that port.

[Problems to be Solved by the Invention] However, in the above-mentioned study technique, only one type of interrupt signal is output from each port side of the dual port memory. Even if you want only one system bus to process interrupts, the interrupt signal is supplied to all microprocessors that share one system bus, so even microprocessors that do not need interrupt processing may have their operations stopped. Invite.

It has become clear that this significantly reduces the data processing efficiency of the system.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dual port memory capable of improving the data processing efficiency of a multiprocessor system in which a plurality of microprocessors share at least one of the system buses coupled to each of the dual ports. be.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, an interrupt request register capable of specifying a microprocessor to be coupled to the other port and storing interrupt request data output from the microprocessor to be coupled to one port, and an interrupt enable/disable state of the other port are provided. a storable interrupt enable register corresponding to a microprocessor to be coupled to such port;
A logic circuit that can specifically supply an interrupt signal formed based on the data stored in both registers to each microprocessor to be coupled to the other port is provided corresponding to each port 1 to 1. It is equipped with an interrupt control circuit.

[For production]

According to the above means, an interrupt request to a desired microprocessor among a plurality of microprocessors sharing one system bus is determined for each microprocessor based on data stored in the interrupt permission register. is determined by a logic circuit,
Selectively transmits an interrupt signal at an interrupt enable level from a system bus side microprocessor coupled to one port to a desired microprocessor among multiple microprocessors sharing the system bus coupled to the other port. The data processing efficiency of the multiprocessor system can thereby be improved.

〔Example〕

FIG. 1 is a block diagram of a multiprocessor system to which a dual port memory according to the present invention is applied.

A dual port memory DI'M that rewritably stores data is coupled to a first system bus SBI and a second system bus SB2 via its first port P1 and second port P2, respectively. The first system bus SBI has
Multiple microprocessors MPuLll to Mpu1i
, a first external data memory DMI, such as RAM (Random Access Memory), and other external devices not shown. The microprocessors Mpu1 to Mpu,i are connected to the first data memory D.
When accessing external devices such as MI and dual port memory DPM, the microprocessor Mpu. ~M
The microprocessor Mpu1 controls which of the pu1i is made to exclusively use the first system bus SBI.
1. A bus arbiter (not shown) that mutually arbitrates requests for exclusive use of the system bus 5131 by Mpuli;
Microprocessor Mpu1. This is performed by a first bus control unit r (C1) which includes a bus controller (not shown) that receives status signals specific to the bus cycles of Mpu1i, decodes them, and outputs predetermined command signals.

A plurality of microprocessors Mpu, a to Mpuzi, a second external data memory DM2 such as a RAM (Random Access Memory), and other external devices are coupled to the second system 11 bus SB2.

The microprocessors Mpu2 to Mpu,L are the data memory DM2 and dual port memory DI.
When accessing an external device such as a microprocessor Mpu,. The microprocessors Mpu2I+ to Mpu□i control which of the microprocessors Mpu2I+ to Mpu2i is allowed to exclusively use the second system 11 bus SR2.
A bus arbiter (not shown) that mutually arbitrates requests for exclusive use of the system bus S This is carried out by a second bus control unit RC2 that includes a bus controller (not shown) that outputs the output.

The dual port memories D, PM have a configuration as will be described later, and are connected to microprocessors Mρ11 . . to Mpu,i and the microprocessors MPIJ2 to Mpu2j sharing the second system bus SB2 are made particularly accessible via the first port pt and the second port P2. In this way, such dual port memory DP
M is 1 like that of general dual port memory.
It is used for exchanging data between the microprocessors on both ports.

The dual port memory DPM of this embodiment processes an interrupt request issued from the microprocessor on one port to the microprocessor on the other port when data exchange is declined. 2
It has an interrupt control circuit INT shown in the figure.

That is, the interrupt control circuit INT has the first .
Second interrupt request register RID1. RID2, first, interrupt enable register RIMI, RIM2, and first. Second
It has circuits LOGI and LOG2. Circuit RI D l, R
I M 1 and L OG l correspond to the first port and have one circuit RID2. RIM2° and r, OG2 are the second
corresponds to the port.

The first interrupt request registers RIDI are each coupled to a first port coupled to the first system bus SBI. The first interrupt request register RIDI is composed of a plurality of bits of data holding means so as to be able to accept a plurality of interrupt requests. Although not particularly limited, the first
Each bit of the interrupt request register RIDt is given a specific address so as to be selected when the address signal supplied via the first port is set to a specific state.

The first interrupt permission register RIMI is coupled to a second port coupled to the second system bus SB2, and has data holding means for the number of bits corresponding to the first interrupt request register IDI. Each bit of the first interrupt permission register RI M 1 is selected by the address No. 43 supplied through the second port.
Each is given a specific address.

The tenth logic circuit LOG1 includes a logic circuit that compares each bit of the first interrupt request register and the first interrupt permission register in a one-to-one correspondence.

As a result, the 10th logic circuit LOG 1 outputs multiple bits, which means the comparison results corresponding to each bit.
)irl is formed.

Such circuits RI D 1, RI M L, and ■,
○By using G1, it is possible to selectively issue an interrupt from the microprocessor connected to the first port side to an appropriate microprocessor among the plurality of microprocessors connected to the second port side. Become. The interrupt request data is stored in a predetermined area of the first interrupt request register RI D l by the microprocessor Mpu, which shares the second system bus SB2. ~M
The first interrupt request register R assigned to pu,,i
This is done by outputting the address signal and interrupt request data on the IDI from the microprocessors Mpouto to Mpu,i. Similarly, the interrupt enable data is stored in a predetermined area of the first interrupt enable register RIMI at an address on the first interrupt enable register RIM1 assigned to the microprocessors Mpu to Mpu2i that share the second system bus SBI. A microprocessor M whose signals and interrupt enable data are
This is done by outputting from pu,a to Mpu,L.

The data stored in the first interrupt request register RIDI and the data stored in the first interrupt request register RIDI
The data stored in the interrupt permission register RIMI is
0-switch circuit LOG1. That is, this tenth switch circuit LOG1 processes the interrupt request data and interrupt permission data for each address assigned to the microprocessors Mpu2D to Mpu, i as a pair, thereby identifying the microprocessor that requests the interrupt and the interrupt requesting data. 1 microprocessor
A one-to-one correspondence is established to determine whether or not the interrupt request can be accepted.

The determination result is supplied to the first decoder circuit DECL as first interrupt control data Dir□ of a predetermined number of bits. The first decoder circuit r)ECI decodes the first interrupt control data D irl and supplies corresponding interrupt signals φi, rQ2o to φ↓r9□i to the respective microprocessors Mρu211 to Mpu2i.

Therefore, when an interrupt request is permitted, an interrupt signal at the interrupt permission level is supplied only to the microprocessor for which the interrupt request has been made.

The circuits RID2, RIM2, and LOG2 are the circuit R
It has the same configuration as IDI, RIMI, and LOG1. As a result, the second interrupt request register RI
Interrupt request data is stored in a predetermined area of D2 by storing the address signal and interrupt request data on the second interrupt request register RID2 assigned to the microprocessors Mpu1 to Mρ1111 that share the first system path SBI. Mpu,. ~M
This is done by outputting from pu2i. Similarly, interrupt permission data is stored in a predetermined area of the second interrupt permission register RTM2 by the microprocessor MρU, which shares the first system bus SBI. Second interrupt permission register R assigned to Mρu0i
The address signals and interrupt enable data on IM2 are transmitted to such microprocessor Mpu! , to Mρu21.

The data stored in the second interrupt request register RID2 and the second
The data stored in the interrupt permission register RIM2 is
The 20th SICK circuit LOG2 is supplied to the 0th SICK circuit LO(E2).This 20th SICK circuit LOG2, like the 10th SICK circuit LOGI, is assigned to the microprocessor Mpu, 0 to Mpu,i. By processing the interrupt request data and interrupt permission data for each address as a pair, the microprocessor that requests the interrupt and the microprocessor that requests the interrupt are made to correspond to L, and it is determined whether the interrupt request can be accepted. The determination result is supplied to the second decoder circuit DEC2 as the second interrupt control data Dir2 having a predetermined number of bits.The second decoder circuit DEC2 outputs the second interrupt control data Dir,
is decoded and the respective microprocessors Mpu, . . .
An interrupt signal φirq□ corresponding to pu1i. to φirq□i are supplied. Therefore, when an interrupt request is permitted, interrupt No. 43 of the interrupt permission level is supplied only to the microprocessor for which such an interrupt request has been made.

Note that the above interrupt signals φ1rQzn to φ1rq2i (
φir9□. to φir9□i) are supplied to the first bus control unit BC1 (second bus control unit IC2), thereby transferring the exclusive right to use the system bus to the microprocessor for interrupt processing when executing interrupt processing. It has become.

Next, the effects of the above embodiment will be explained.

(1) Microprocessors Mpu1o to Mpu1i (M
Pu! . Mpu2i) to the other system bus 5B
Interrupt requests to microprocessors Mpu2゜ to Mpu,i (Mpul, to Mpu,i) that share SBI 2 (SBI) are sent to the interrupt permission register RIMI (RI
Based on the data stored in the logic circuit LOG1(
LOG2), and the interrupt signals φ1rq2゜ to φirq,i (φ1rQto to φ1rq1i) based on the determination results are sent to the microprocessors Mpu2゜ to M
Pu2x (Mpu□. to Mρu1i) is specifically supplied. Therefore, when an interrupt request is permitted, an interrupt signal at the interrupt permission level is supplied only to the microprocessor that has received the interrupt request, so microprocessors that do not require interrupt processing can continue their control operations. Can be done.

(2) As a result of the above effects, it is possible to improve the data processing efficiency of a multiprocessor system in which a plurality of microprocessors are coupled to at least one of the system buses connected to each port.

(3) In particular, the microprocessor Mpu1. ．． ~Mp
Interrupt signal φirq, which is directly supplied to u□i (Mpu, . to Mpu2i). 〜φirq 工i(φ1r(1
2o to φ1rq2i) are the logic circuit LOGI
Since it is formed by an external decoder circuit based on the interrupt control data output from (LOG2), it has versatility with respect to the number of microprocessors included in the system to which the dual baud 1 to memory DPM is applied.

Dual port memory required for interrupt control DI)M
The number of external terminals can be minimized.

Although the invention made by the present inventor has been specifically explained above based on examples, the present invention is not limited to the above-mentioned examples, and various changes can be made without departing from the gist thereof.

For example, the interrupt request register and interrupt permission register in the above embodiment are configured to compare interrupt request data and interrupt permission data in a one-to-one correspondence for each microprocessor to determine whether interrupt processing is possible. It is not limited to that.

By configuring the interrupt request data and interrupt permission data as data of a predetermined number of bits including contents regarding the interrupt source and interrupt request destination, the scale of each register can be reduced. For example, the upper predetermined bits can be used as data regarding an interrupt source or interrupt request destination, and the lower predetermined bits can be used as interrupt content data. Further, in the above embodiment, the interrupt signal is output to each microprocessor via the decoder circuit, but the interrupt signal may be output directly from the logic circuit.

In the above explanation, the invention made by the present inventor is mainly applied to a multiprocessor system in which a plurality of microprocessors are coupled to each system bus, which is the technical field behind the invention, but the invention is limited thereto. Rather, it can be widely applied at least to systems in which a plurality of microprocessors are connected to one port via a system bus.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

That is, when multiple microprocessors are connected to one port, the microprocessor to be connected to the other port interrupts only a selected predetermined microprocessor to be connected to one port. Since it includes an interrupt control circuit that allows processing to be accepted, it is possible to have only the desired microprocessor among multiple microprocessors that share the system bus perform interrupt processing, and it is useful for microprocessors that do not require interrupt processing. By maintaining the control operation, it is possible to improve the data processing efficiency of the multiprocessor system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiprocessor system to which a dual port memory according to an embodiment of the present invention is applied, and FIG. 2 is a block diagram of an interrupt control circuit. DPM...dual port memory, Pl...first port, P2...second port, SBI...first system bus, Sn2...second system bus, Mpui. to MρuIL... microprocessor, Mpu2o to Mpu2i... microprocessor, INT...
Interrupt control circuit, RIr)]...Second interrupt request register, RID2...Second interrupt request register, RIM
I...first interrupt permission register, RTM2...second
Interrupt permission register, ■, OG1... 10th chic circuit, ■, OG2... 20th chic circuit, φirq□
. to φirq, i...first interrupt signal, φirq
□1. to φirq, i... second interrupt signal.

Claims (1)

[Claims] 1. A dual port memory applicable to a multiprocessor system in which a microprocessor is coupled to each of the dual ports via a system bus, wherein a plurality of microprocessors are coupled to at least one port. A dual port characterized in that it includes an interrupt control circuit that causes only a predetermined one of the microprocessors to be connected to one port to accept interrupt processing from a microprocessor to be connected to the other port when the dual port is connected to the other port. memory. 2. The interrupt control circuit includes an interrupt request register capable of specifying a microprocessor to be coupled to the other port and storing interrupt request data output from the microprocessor to be coupled to one port; An interrupt enable register that can store the interrupt enable/disable state of a port in correspondence with the microprocessor to be coupled to the port, and an interrupt enable register for each microprocessor to be coupled to the other port, based on the data stored in both registers. 2. The dual port memory according to claim 1, wherein a logic circuit is provided corresponding to each port, and is capable of specifically supplying an interrupt signal.