JPS62272345A - Bus arbitrating system - Google Patents

Abstract

PURPOSE:To equalize priority levels of bus use of respective modules by constituting bus use permission signal lines, which connect respective modules, into a ring. CONSTITUTION:When a module a11 uses a bus, a bus arbitrating circuit 1a in the module a11 has the bus use permission right (the right by which a bus use permission signal *BG is generated). When a module c13 issues a request signal *RQ, the bus arbitrating circuit 1a receives it. The module a11 issues the bus use permission signal *BG after terminating the use of the bus, and the bus use permission signal *BG is temporarily received by a module b12 and is transferred to the module c13 as it is. Thus, the module following the module which uses the bus at present has the highest priority level of bus use and priority levels of bus use of modules are lower counterclockwise in order, and the bus use right is equally given to respective modules if operation states of all modules are averaged.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a bus arbitration method using a so-called daisy chain, and particularly relates to a bus arbitration method that averages the priorities of using buses. .

[Conventional technology]

Conventionally, a bus arbitration method has been used in which the bus use permission signal line is daisy-chained. An example of this is shown in FIG. In the figure, l is a bus arbitration circuit that determines which module is allowed to use the bus, 2 is a bus, and 3 is a request signal line through which each module requests use of the bus, and sends a request signal *RQ. Forward. 4 is a bus use permission signal line, through which the bus arbitration circuit 1 transfers a bus use permission signal *BG that allows each module to use the bus.

1112.13 are modules sharing the bus.

In FIG. 2, when one of the modules issues a bus use request signal *RQ, the bus arbitration circuit 1 issues a bus use permission signal *BG to line 4 if the bus is not in use. Each module uses this bus use permission signal *BG
If the receiver issues the quest signal *RQ, it will monopolize the bus, and if it does not issue the request signal *RQ, it will transfer the bus permission signal *BG to the next module.

[Problem that the invention seeks to solve]

However, in the conventional system, the module 11. shown in FIG.
12. Among 13, if the request signal *RQ is issued at the same time, the bus use permission signal lines are daisy-chained, so the closer to the left the higher the priority is for using the bus, and the closer to the right the higher the priority. There was a problem in that the priority of using the bus was biased depending on the hardware configuration.

The present invention solves the above problems and provides a bus arbitration system that allows each module to have equal priority in bus use.

[Means for solving problems]

In order to solve the above problems, the present invention provides a bus arbitration system having a plurality of modules, a bus shared by the modules, a bus arbitration circuit, a bus use permission signal line, and a daisy chain bus use permission signal line. In this method, a bus arbitration circuit is provided for each module, the bus arbitration circuit in the module using the bus is granted permission to use the bus next, and the bus permission signal line is arranged in a ring shape. A bus arbitration method is provided.

[Effect]

The bus arbitration circuit in the module currently using the bus has the right to grant permission to use the next bus, and the priority for using the bus starts with the module following the module currently using the bus having the highest priority and decreasing in order. Accordingly, if all the bus usage operations of each module are averaged, the priority of bus usage will be averaged and become equal for each module.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention. In the figure, 1 is a bus arbitration circuit, and as shown in the figure, the same bus arbitration circuit 1a, lb, IC and l are provided for each module.
d, and there is no comprehensive bus arbitration circuit that controls the entire system.

2 is a bus shared by each module, which is configured in a ring shape as shown in the figure. 3 is a request signal line, each module outputs a request signal *RQ, and is configured in a ring shape as shown in the figure. Reference numeral 4 denotes a bus use permission signal line, which is arranged in a daisy chain form from one module to the next module, and in a ring form, as shown in the figure. 11.12.13 and 14 are modules that use the bus, and if you want to use the bus,
If a request signal *RQ is issued and use of the bus is approved, the bus can be used.

Next, the operation of the embodiment shown in FIG. 1 will be described.

Assume that module all is currently using the bus. The bus use permission m (the right to generate the bus use permission signal *BG) is held by the bus 8 requirement circuit 1a in the module a.

Next, when module C issues a request signal *RQ,
This signal is received by the bus arbitration circuit 1a which holds the right to permit use of the bus. When the module la finishes using the bus, it issues a bus use permission signal *BG.The bus use permission signal *BG is once received by the module b12, and since the module b12 has not issued the request signal *RQ, it remains a module. Transfer to c13. Module c13 receives this signal and is able to use the bus.
At the same time, the bus arbitration circuit 1c in the module C13 holds the right to permit use of the bus. In this way, bus usage is assigned to each module.

Also, module all uses the bus, and module b12 and module c13 simultaneously receive the quest signal *
When you get RQ, Eju.

When all has finished using the bus, the bus arbitration circuit 1a outputs a bus use permission signal *BG, and the module b12 that has passed this signal uses the bus and at the same time has the right to use the bus.

In this way, since the modules are connected in a ring shape, the priority for using the bus starts with the highest priority for the module following the module currently using the bus, and gradually decreases in the counterclockwise direction. Therefore, if all operating states are averaged, all modules will be given the right to use the bus fairly, and there will be no bias due to hardware configuration.

In the above description, the number of modules is four, but this number can be increased or decreased as desired.

〔Effect of the invention〕

As explained above, in the present invention, the arrangement of each module,
In particular, since the bus permission signal line connecting each module is arranged in a ring shape, the bus usage priority is equal for each module, and the delay time of the bus permission signal is averaged.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional daisy chain bus arbitration system. 1 as 1 bs 1 cs 1 d---4il
l Stop circuit 2 --- Bus 3 --- Request signal line 4 --- Bus use permission signal line 11.12.13.14 --- Module applicant
FANUC Co., Ltd. Agent Patent Attorney Takeshi Hattori Figure 1

Claims (1)

[Claims] A plurality of modules, a bus shared by the modules,
In a bus arbitration method having a bus arbitration circuit, a bus use permission signal line, and a daisy chain bus use permission signal line, a bus arbitration circuit is provided for each module, and the bus arbitration circuit is provided for each module, and the A bus arbitration method, characterized in that a bus arbitration circuit is given permission to use the bus next, and the bus permission signal line is shaped like a ring.