KR950009574B1 - Memory access controller - Google Patents

Abstract

The memory access control device enhances the system speed by implementing the bus arbitrator and the shared memory access control circuit on programmable logic array(PLA). The device comprises a bus arbitrator(100) for endowing the system bus controllability to several masters(80,90) according to the data access request signal for a shared memory(50); a multi-bus exchange(MBE) unit(120) for setting the data routing path to several masters(80,90) to transmit the data from the shared memory(50) to the masters(80,90); an MBE control unit(110) for controlling the MBE(120) unit to determine the data routing path.

Description

Memory access control

1 is a conventional memory access control apparatus.

2 is an embodiment of a memory access control apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

10: central processing unit 20: master unit

30: first hardware glue logic unit 40: second hardware glue logic unit

50: shared memory 60: data buffer

70: memory controller 80: first master portion

90: second master unit 100: bus adjustment unit

110: MBE (Multi Bus Exchage) control unit

120: Multiverse Exchange Department

The present invention relates to a memory access control device in a multimaster system, and more particularly, to a memory access control device for a shared memory.

In general, when there are a lot of peripheral devices such as I / O devices, the multi-mast system is a system for processing them. In other words, the processor is placed on the master to control and process the system's commands and data with the input / output device.

1 is a memory access control device in a conventional multimaster system.

In FIG. 1, the configuration relationship shows that the central processing unit 10 controls all devices of the system and executes commands, and transfers control of the system bus from the central processing unit 10 to the shared memory 50. After receiving the master unit 20 performing the access, the request signal REQUEST of the master unit 20 and the bus permission signal BUS_GRT of the CPU 10 as inputs, the bus acknowledgment signal BUS_ACK is received. After receiving the address and the control signal from the first hardware glue logic (30) consisting of a TTL (Transistor Transistor Logic) logic element to generate, and the central processing unit 10 or the master unit 20 as an input The memory controller 70 generates a buffer control signal, and the second hardware glue logic unit 40 determines whether to enable or disable the data buffer 60 and the like.

Referring to the operation of Figure 1 as follows.

When the master unit 20 wants to access the shared memory 50 of the system, the master unit 20 applies a request signal REQUEST to the first hardware glue logic unit 30. When the first hardware glue logic unit 30 receives a REQUEST signal of the master unit 20, that is, a signal for requesting data access from the shared memory 50 as an input, the system bus request signal (BUS_REQ) is transmitted to the CPU 10. ) Is applied. When the CPU 10 receives BUS_REQ as an input, the CPU 10 terminates the currently running process and enters an idle state. The CPU 10 then applies a system bus permission signal BUS_GRT. The first hardware glue logic unit 30 applies a bus recognition signal BUS_ACK indicating that the master unit 20 has obtained the control right of the system bus. When BUS_ACK is applied, the master unit 20 outputs an address and a control signal to execute access to the shared memory.

The second hardware glue logic unit 40 enables the data buffer 60 by using the buffer control signal output from the memory controller 70. The data buffer 60 outputs the data to the master unit 20 in accordance with the enable signal that the data accessed from the shared memory 50 is temporarily stored by the address output from the master unit 6.

After all accesses to the shared memory 50, the master unit 50 passes the control right to the central processing unit 10 by canceling the REQUEST signal. The central processing unit 10 having obtained the control right for the system bus performs a normal data transfer operation.

However, in the conventional memory access control apparatus, when the number of masters increases, there is a difficulty in hardware redesigning the second hardware glue logic unit 40 that enables the first hardware glue logic unit and each of the separate data buffers. As the complexity increases, the gate used increases. As the number of gates increases, the gate delay increases, which affects the speed of the system and exposes more to external noise.

Accordingly, an object of the present invention is to solve the above problems, the memory access control apparatus that can improve the speed of the system by configuring the control of the bus control and the shared memory access to a plurality of masters to the programmable array logic (Programmable Array Logic) In providing.

In order to achieve the above object, a memory access control apparatus in a multimaster system receives a data access request signal of a shared memory as input from a plurality of masters, and programmatically controls a bus arbitration unit (Bus Arbitration). )Wow; A multiple bus exchange unit (hereinafter referred to as MBE) for establishing a data routing path to each master for outputting data accessed from the shared memory to the plurality of masters; It characterized in that it comprises an MBE control unit for determining the data path by controlling the MBE.

Hereinafter, with reference to the accompanying drawings will be described in detail with respect to the present invention.

2 is an embodiment of two masters as a memory access control apparatus according to the present invention.

In FIG. 2, the configuration relationship shows a central processing unit 10 for controlling all devices of the system and executing commands, a first master unit 80 for controlling external input / output devices and executing commands; A memory that receives an address and a control signal from the second master unit 90, the central processing unit 10, the first master unit 80, and the second master unit 90 as an input, and generates a buffer control signal. The shared memory 50 in which the controller 70, the central processing unit 10, the first master unit 80, and the second master unit 90 share data or instructions in common, and the first master unit 80. And a bus adjusting unit 100 which receives the request signal REQUEST of the second master unit 90 and the bus permission signal BUS_GRT of the CPU 10 as an input and generates a bus easy BUS_ACK. Enabling the data buffer and controlling the MBE by receiving the buffer control signal as input from the controller 70 An MBE control unit 110 and a multiverse exchange unit 120 for setting a data path by outputting data accessed from the shared memory 50 to the first master unit 80 and the master unit 90. do.

Next, operation of FIG. 2 will be described.

When the first master unit 80 and the second master unit 90 want to access data or instructions contained in the shared memory 50 of the system, each request signal REQ_1 or REQ_2 is transmitted to the bus controller 100. Allow it. When the request signal is applied, the bus adjusting unit 100 applies the bus request signal BUS_REQ to the CPU 10.

When the bus request signal BUS_REQ is active, the CPU 10 ends the currently running processor and becomes idle. Next, the central processing unit 10 applies a bus permission signal BUS_GRT to the bus controller 100 to use a system bus.

When the bus permission signal BUS_GRT is active, the bus adjustment unit 100 outputs the bus recognition signals ACK_1 and ACK_2 after performing arbitration of the bus control right according to the programmed method.

Priority and round-robin methods are mainly used to determine the control right of the system bus when a plurality of masters simultaneously grant access request signals to the shared memory. When the control right of the system bus is determined, the master unit having the control right of the system bus activates a control signal necessary for accessing the address and the shared memory 50.

If the control right of the system bus is determined to the second master unit 90, the bus adjusting unit 100 outputs a bus recognition signal ACK_2. The second master unit 90 applies an address and a control signal to the memory controller 70. In the shared memory 50, data corresponding to the address of the second master unit 90 is accessed. The MBE controller 110 determines an output path of data accessed to the multiverse exchange unit 120 using the buffer control signal output from the memory controller 70. The multiverse exchange unit 120 sets a data output path and outputs the data accessed from the shared memory 50 to the second master unit 90.

The multi-bus exchange unit 120 is composed of a plurality of ports, and serves as a kind of link for determining the output path by external control signals and outputting the input data in various ways.

After completing the access to the shared memory 50, the master unit 80, 90 cancels the request signal and the bus adjusting unit 100 grants the central processing unit 10 the control right of the system bus. The CPU 10 performs normal operation until the bus request signal BUS_REQ is applied again.

As described above, according to the present invention, even if the number of masters is increased by implementing the bus controller using the PAL, the control right selection method and priority of the system bus can be changed by changing only the logic of the PAL- without changing the hardware logic. In addition, since the bus control unit and the multi-bus exchange unit are configured in one PAL, the system can increase the speed of the system by minimizing the gate delay.

Claims (3)

In the multi-master system, a bus arbitration 100 for receiving data access request signals of the shared memory 50 from a plurality of masters 80 and 90 as an input and programmatically granting control to the system bus. ; Multi-bus exchange unit for setting a data routing path to each master (80, 90) to output the data accessed from the shared memory 50 to the plurality of master (80, 90) And a multiple bus exchange (hereinafter referred to as MBE), and an MBE controller (110) for controlling the MBE (120) to determine a data path. The memory access control apparatus of claim 1, wherein the bus priority unit determines a control priority of a system bus based on a round robin method. The memory access method of claim 1, wherein the bus adjusting unit 100 and the multi-bus exchange unit 120 are configured as programmable array logic to facilitate a change of logic according to an increase in the number of masters. Control unit.