JPS59218532A - Bus connecting system - Google Patents

Abstract

PURPOSE:To improve the operating rate by connecting a multiprocessor to a bus line of a tree constitution and using a bus connecting device provided at a branching part to attain the upper bus occupation for each branch, a procesor within a branch or a lower branch. CONSTITUTION:Bus connecting devices 121 and 123 are provided to a main bus 11 for connection of slave buses 131 and 133, and the bus 131 is connected to a sub-slave bus 132 via a bus connecting device 122. Then processors 17 and 18, a shared memory 16, a signal processing control processor 14, a signal processor 15 and work memories 191-192 are connected to the buses 11 and 131-133, respectively. The devices 121-123 are controlled to occupy the bus for each branch and to make a processor within a branch or a processor of a lower branch occupy an upper bus. This attains a partial parallel operation and improves the overall operating rate.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a bus connection system that prevents a reduction in the operating time of each processor due to competition for occupying a pass line in a multiprocessor system that shares pass lines.

[Background of the invention]

As shown in Figure 1, a multiprocessor system that shares path lines has a single path line 1 that is common to the entire system, and each processor 41゜'2+'B issues a pass line occupancy request and determines whether or not it can be occupied. The processor using path line 1 uses pass line 1, and the other processors wait until they can be occupied.

However, the sharing of the pass line in this 5 form is...

If most of the operations of each processor are performed without using the shared bus and the shared bus is occupied only when accessing the shared memory 5, this is not much of a problem. 5. In large-scale systems that require reference to 5, systems that add high-speed signal processing additional processors to shared path lines and process data by transferring data using DMA, the following problems may occur. arise.

■Conflict for occupation of the pass line occurs between processors, making it impossible for multiple processors to operate side by side.

■Since the memory space of each processor is common,
There is not enough address space available for exclusive use by individual processors.

■Pass line occupancy processing is performed, for example, by the digit chain method shown in Figure 1, but there are problems such as strict regulation of response timing to bus requests, and it is difficult to connect a large number of processors with a pass line. is difficult.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus connection system that eliminates the drawbacks of the prior art described above, improves the operating time of individual processors, and expands the address area that can be used exclusively by each processor.

[Summary of the invention]

The misfiring BA configures the pass lines in a tree shape, and first performs pass line occupancy processing for each sheet.-1 After that, it determines the necessity of occupying the upper pass line and issues a pass line occupancy request. , this allows an individual processor, even if it is at the end of a dendritic bus, to occupy higher and higher path lines as needed, and to occupy a limited range when not needed. [Embodiments of the Invention] The present invention will be described below with reference to embodiments shown in the drawings.

FIG. 2 is a conceptual diagram of the present invention. Reference numeral 7 is a main bus serving as a trunk, and this main bus 7 has a branch-like local bus 8.
．． ~8. is connected, and local bus 8. A local bus 84 is further connected to. 9. ~98 is a processor; 10. ．． 102 is a shared memory.

FIGS. 5(a) and 5(b) show two embodiments using the bus connection method according to the present invention. In the same figure (a), when the signal processing device 15 is a high-speed circuit, if the main bus 11 and the local path 15 are common, the main bus 11 is
In order to prevent the processors 17 and 18 from remaining in a stopped state due to
A bus connection device 12 is provided between the local bus 13 and the local bus 13,
This is an example in which the signal processing device 15 is separated from the main bus 11 when necessary. Note that 14 is a control processor for signal processing, and 16 is a shared memory.

In addition, the signal processing device 15 itself is separated from the signal processing control processor 14 by the bus connection device 122 to enable parallel operation with the signal processing control processor. Processor 18 also connects bus connection device 123 to main bus 11.
It is separated from the processor 17 so that it can operate without conflict with the processor 17. 13°～13. is a local bus, 19
．． ．． 192 is a work memory.

Among the configurations shown in FIG. 3, bus connection devices 12, 12 . .

12,. 12. The rest can be fully realized by assuming well-known devices such as Intel's multipath specifications and computer boards and memory boards made according to the specifications, so the bus connection device will be described below.

FIG. 4 is a principle diagram of a bus connection device compatible with Intel's multipath. In the figure, 21 is an address analysis/main bus occupancy determination circuit (PLA1) that checks the pattern of the segment address signal (upper 4 bits of the address line) 53 and detects only the local bus shown on the left side of the figure in segment units. It is determined whether the main bus side shown on the right side of the figure is occupied, and if it is necessary to occupy the main bus side, the request signal (RFjQ) 56 is determined.
issue. This signal is valid when there is a read signal (MRDC) 31 or a write signal (MWTC) 32, so these signals are ORed by the OR element 23 and ANDed by the AND element 24. , issues a request signal to the main bus occupancy request circuit 22. This circuit is a circuit that performs basic multipath occupancy processing, and outputs a bus request signal (BREQ) 41 and a bus occupancy permission signal (BP).
This is a circuit that follows the multipath convention and waits for RN) 38.

When a bus occupancy request is accepted, this circuit sends an occupancy signal (
REV) 42 is output, and the signal on the local bus side is
It is placed on the main bus side via the state line driver 25 and performs necessary operations.

Note that the occupancy process on the local bus side is performed independently on the local bus side. This process is performed by the bus occupancy permission circuit 20 on the connected device, but in the multipath basic mode, it is as simple as simply returning the bus request signal (BREQ) 41 to the bus occupancy permission signal (BPRO) 38. It is.

In addition to the signals mentioned above, there are clock signals, acknowledge signals, etc., but these are not included because FIG. 4 is a diagram of the principle. Bus occupancy is released using an acknowledge signal.

In FIG. 4, 34 is an address signal, 35 is a data signal, 37 is a common bus request signal, 39 is a bus request acceptance output signal forming a digit chain with the bus occupancy permission signal 38, and 40 is a bus busy signal.

〔Effect of the invention〕

According to the present invention, the bus of a multiprocessor can be divided and controlled in necessary units, so that the following effects can be obtained.

(1) Since bus occupancy processing can be performed independently for each divided path line, the timing regulations for occupancy signals only need to be followed for each divided bus, and are assembled into a tree. By combining these, a large number of processors can be connected by path lines.

(2) Signal processing (especially image processing that requires a large amount of memory)
Even when a processor that occupies the bus heavily, such as a high-speed processor, is operating, the operation of other processors is not hindered, and the operation of the entire system can be ensured. Incidentally, the bus occupancy time when processing a 256×256# plain grayscale image lasts for 16 milliseconds without interruption, and if other processors cannot operate during this time, it will have a large impact on real-time control.

(3) The memory space on the local bus side is a unique space completely unrelated to the main bus side, and each processor can take up any space on the local bus side.

Therefore, compared to the case where the bus is not divided, the space that can be used exclusively by each processor can be greatly expanded.

(4) Since bus occupancy processing is performed on a divided bus basis, rules regarding signal conditions are less strict.

It becomes possible to include a large number of processors in the system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a general multiprocessor system. FIG. 2 is a conceptual diagram of a bus connection device according to the present invention configured in a tree shape. FIG. 3 is a block diagram of two embodiments of the present invention. FIG. 4 is a specific configuration diagram of the bus connection device shown in FIG. 3. 7.11: Main bus, 12.12.~12.: Bus connection device. 15.13.~13□: Local bus. 14: Control processor for signal processing, 15: Signal processing device, 16: Shared memory, 17.18 Two processors, 19. .192: Memory for '7-ri.

Claims (1)

[Claims] In a multiprocessor system connected by path lines, the path lines are arranged in a tree shape, and a bus connection device is provided at each branch, so that each branch occupies a bus, and the processors in the school or lower branches connect to the upper one. A bus connection system characterized in that when a bus is required, a higher level bus is occupied via the bus connection device.