JPH03188553A - Dual bus system for multiprocessor system - Google Patents

Abstract

PURPOSE:To improve the high-speed performance of buses by dividing a main memory with an address and connecting them to the corresponding system bus to attain the simultaneous accesses to two main memories of a processor. CONSTITUTION:A 1st bus forming a 1st system bus 1 is provided together with a 2nd system bus 5 which secures connection between a processor and a main memory 6. The memory 6 is divided into 1st and 2nd main memories 10 and 11 via an address. These memories 10 and 11 are connected to the buses 1 and 5 respectively. When the processor has an access to the memory 6, the buses 1 and 5 connected to the memories 10 and 11 are selectively acquired with an address to give an access to the memory 6. Thus the simultaneous accesses are available to both divided memories. Thus, the high-speed performance is improved for both buses 1 and 5.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a dual bus system in a multiprocessor system.

[Conventional technology]

Conventionally, in the dual bus system aimed at solving bus problems in multiprocessor systems, multiple processors, main memory, Ilo, etc. are connected in the same way to two system buses with the same function, and each bus has one Generally, the main memory (1) has a function to arbitrate simultaneous accesses from two buses and perform exclusive control.

[Problem to be solved by the invention]

In the dual bus method described above, the main memory, ■/○
Exclusive control within the system is complex, and although bus problems can be resolved to some extent, simultaneous access to different addresses in main memory is impossible, so when running software that frequently accesses main memory. had the disadvantage that it was not very effective.

[Means to solve the problem]

The dual bus method of the multiprocessor system of the present invention is such that, in a multiprocessor system consisting of a plurality of processors, a system multibus is provided with a first bus and a second bus connecting the processor and the main memory, and the main The memory is divided into a first main memory and a second main memory based on addresses, each of which is connected one-to-one to the first and second buses, and when the processor accesses the main memory, The configuration is such that the first and second buses to which the first and second main memories are connected are selected and acquired to perform memory access, thereby enabling simultaneous access to the divided memories.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1, 2, and 3 show an embodiment of the present invention.

Here, the explanation will be given assuming that the number of processors in the multiprocessor system is three. 1 is a system bus of a multiprocessor system; 2. 3. 4 is M with a processor
PU block, 5 is the second system bus, 6 is the main memory block, 7fI10 block 8.9 is the bus controller, 10 is the memory 1 consisting of even address memory
．． 11 is memory 2.12 consisting of memories with odd addresses.
1 is a microprocessor, and 13 is a bus selection circuit. Main memory 6 needs to be divided into memory 1 and memory 2 in order to connect one to each of the two system buses.
system bus1. In this case, even numbers and odd numbers are used so that the usage rate of 5 is the same regardless of the software running, but the division is optimized according to the main memory access characteristics of the system. When the CPU 12 of a certain MPU block accesses an even address in the main memory 6, the bus selection circuit 13 in the MPU block selects the necessary bus from the memory or I10 signal and address signal from the CPU 12 (in this case, the system bus 1 ), sends a bus request to the bus controller controlling the bus, and performs access after a bus acknowledge is returned. Similarly, when accessing an odd address, system bus 5 is selected. Therefore, simultaneous access to odd addresses, Ilo, and even addresses of the main memory 6 is possible.

〔Effect of the invention〕

As explained above, according to the present invention, by dividing the main memory by address and connecting it to the corresponding system bus, it is possible to simultaneously access the main memory and the main memory of two processors, or the main memory and the 110. , it can be applied to a multiprocessor system to improve its economy and bus speed.

...■10 blocks, 8.9...Bus controller, 10-...Memory l, 11...
Memory 2.12...CPU, 13...
Bus selection circuit.

Claims (1)

[Claims] In a multiprocessor system consisting of a plurality of processors, a first bus forming a system bus and a second bus connecting the processor and a main memory are provided,
The main memory is divided into a first main memory and a second main memory based on addresses, each of which is connected one-to-one to the first and second buses, and when the processor accesses the main memory, the main memory is divided into a first main memory and a second main memory. A dual processor system of a multiprocessor system which selects and acquires the first and second buses connected to each of the first and second main memories, performs memory access, and enables simultaneous access to divided memories. Bus method.