JPH04659A - Computer board - Google Patents

Abstract

PURPOSE:To execute the parallel processing of a CPU, and also, to simplify the data exchange between CPUs by constituting the computer board so that a multi-port bus connected to a multi-bus of the outside of a printed board is provided, and each processor shares resources through the multi-port bus. CONSTITUTION:In a printed board 1, CPUs 11-13 and a ROM 14, a RAM 15 and an I/O 16 being resources are placed in a multi-port bus 2, and the multi- port bus 2 is connected to a multi-bus 3 of the outside of the printed board 1. Accordingly, when the multi-port bus 2 is used, and each CPU 11-13 has no priority and accesses the same resources, for instance, a memory 14, while executing each different work, the priority is delivered alternately, and the parallel processing of the CPUs 11-13 can be executed. In such a way, the parallel processing of the CPUs 11-13 can be executed, and the data exchange between the CPUs 11-13 can be simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION A. Industrial Application Field The present invention relates to a computer board having a processor (hereinafter referred to as a CPU) mounted on a printed board, and in particular a computer board having a plurality of CPUs mounted thereon. Regarding the circuit configuration.

B1 Summary of the Invention The present invention provides a computer board with a plurality of CPUs mounted on a printed board, which includes a multi-port bus connected to a multi-bus outside the printed board, and each processor accesses resources via the multi-port bus. By sharing the C
Eliminate local buses and replace multiple C busses without increasing
It provides a technology for PUs to share memory.

C0 Prior Art When a plurality of CPUs are mounted on a printed circuit board, the circuit configuration of the computer board can usually be configured in one of the following two ways.

FIG. 7 is a configuration diagram of an example of a shared bus interface method. In the figure, 7I is CPU, 72 is Co-CPU
, 73 is a CPU bus, 74 is a ROM, 75 is a RAM, 7
6 is Ilo, when the Co-CPU 72 uses the CPU bus 73, the CPU 71 hands over the CPU bus 73.

This method is basically dual port access.

FIG. 8 is a configuration diagram of an example of a multi-bus/dual-port interface system. In the figure, 81a to 81n
are a plurality of CPU boards, and the CPU, memory, and Ilo are connected to local buses 82a to 82n on each board, and the local bus 82n is connected to a multibus 83.

In this case, the CPIJ on each board can access local memory on other ports through the multibus 83. This method is also dual port access.

09 Invention or problem to be solvedHowever, in the above conventional system, three or more CPUs
If you try to access the same bus, the following problem will occur. First, in the system shown in Fig. 7, CPLis are 1 to 1.
Since it is an interface that supports multiple ports, it is impossible to increase the number of CPUs.In the method shown in FIG. , there is a risk that costs will also increase.

When two CPUs are mounted on one CPU board, if the shared bus interface method 111 shown in FIG. 7 is used, Co-CPL! If you want to access CPU 72 or CPU 3, be sure to write “HOL D” to CPU 71.
” is commanded, and the CPU 71 enters the waiting state.
In a system where each CPTJ and Co-CPU perform different tasks at the same time, priority is always given to the Co-CPU, and as shown in Figure 9, the Co-CPU can execute the task without waiting. On the other hand, since the CPU is always in the "HOLD" state, it is virtually as if the CPU does not exist. On the other hand, the multi-bus/dual-port interface method shown in FIG. 8 is a method of adding a CPLI board 81n, and therefore cannot be used in this case.

The present invention was created in view of these problems, and
It realizes parallel processing of CPUs, simplifies data exchange between CPUs, and realizes resources by accessing from multiple directions.It eliminates the local bus without increasing the number of actual devices, and allows multiple CPUs to use memory. Its purpose is to provide a shareable computer board.

E Means for Solving the Problems The means for solving the above problems in the present invention are as follows:
As shown in the figure, which also serves as an embodiment and shows the basic configuration, a printed board 1 includes a plurality of processors 11 to 13 and each resource 14.1.
In a computer board equipped with 5.16,
The computer board includes a multiport bus 2 connected to a multibus 3 outside the printed board 1, and each processor 11 to 13 shares resources 14, 15 or 16 via the multiport bus 2. . Note that among the resources, I4 is ROM, and 15 is RAM.

16 is Ilo.

F. Function The present invention uses a multi-port system, and as shown in the timing diagram in Figure 2, each CPU does not have a priority and performs different tasks, but when accessing the same resource, such as memory, it is used alternately. For example, CPJJ
2 causes the CPU 2 to wait only while accessing the multi-port bus, and conversely causes the CPU 2 to wait while the CPU 2 is accessing the multi-port bus, thereby enabling parallel processing of the CPUs.

Generally, in a computer system, as shown in FIG.
The M32 and the RAM 33 for storing data are connected to the local bus 34 of the CPU, and when data is to be exchanged between the CPUs, data is exchanged via the gate 35 disposed between the local buses and the local bus 34 of each other. , each memory is accessed. If this continues, as in the conventional example, the only option would be to "WAIT" one of the CPUs and use the other CPU to access it during that time, making parallel processing impossible, and even that becomes difficult when the number of CPLs increases to three or more. It is well known that

Therefore, in the present invention, a multi-port bus is provided between the local buses of each CPU shown in FIG. There is no "HOLD" operation, and the multiport bus only needs to be accessed when data needs to be exchanged.

G. Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a configuration diagram showing an embodiment that also serves as the basic configuration of the present invention, in which 1 is a printed board forming the computer board of the present invention, 2 is a multiport bus, and 3 is a multibus. . Inside the printed board l are CPUs 11, 12 and 13, and resources ROM 14 and RAM 1.
5 and l1016 or multiport bus 2,
The multiport bus 2 is connected to a multibus 3 outside the printed board 1. Each of the processors II to 13 shares resources 14, 15, and 16 via the multiport bus 2.

FIG. 4 shows a configuration in which memory and Ilo resources are connected to the multiport bus, and multiple CPUs can be used equally for each of the CPUs (CPU1...
Control circuits 41, 4 for CPU2 and CPL'3)
2.43 is arranged, and each arbiter circuit (hereinafter referred to as MPB arbiter circuit or MB
(abbreviated as Archita circuit) 44.45 are arranged.

Note that a sequencer may be used instead of the CPU.

FIG. 5 shows a concrete and detailed example by combining both the configurations of FIG. 1 and FIG. 4. In the figure,
1 is the CPU port, 2 is the multiport bus, 3 is the multibus, and multiport bus 2 is the multibus 3 outside the board.
connected to the first to third CPUs (CPU ports) 5
1,52.53 and ROM54. RAM55. l105
6 is connected. Control circuits 57, 58, 59 are attached to the CPUs 51, 52, 53, respectively, and send a ready signal RDY to the MPB archita circuit 60.
A bus request signal CPnRQ is sent to. MPB
The Arhita circuit 60 outputs the bus permission signal CP of that CPU number.
Reply nEN. The MPB arbiter circuit 60 also receives the multibus request signal MB from the MB arbiter circuit 61.
Upon receiving the RQ, the bus permission signal MBEN is sent back. The MB arbiter circuit 6I sends a request signal CBRQ for another CPU board to the multibus 3, and the multibus 3 returns a disallowance signal BUSY when the requested CPU board is occupied.

The CPU control circuits 57, 58, and 59 control each CPU.
When a request for access to the multi-port bus 2 is issued, a request signal CPnRQ is output to the MPB arbiter circuit 60, and the CPU is set to "WA" until the bus permission signal CPnEN is returned.
When the hash permission signal CPnEN is returned, the circuit opens the gate of the multiport bus 2 and puts the CPU in the "RDY" state to perform access.

It corresponds to the interface between the CPU and the MPB arbiter circuit.

The MPB arbiter circuit 60 is connected to the CPU 51, 52 or 53.
When attempting to access multiport bus 2, CP
Each CP receives a bus request signal CPnRQ from U.
The bus permission signal CP is set so that U has an equal bus occupancy rate.
This is a circuit that sequentially returns nEN to each CPU.

For example, as shown in FIG.
When trying to access the CPU (CPU2) or Multibus 3, interface with Multibus,
This is a circuit that returns a bus permission signal CPnEN to the CPU 2 when the right to use the multibus 3 is acquired, and also sends a request signal MBRQ to the MPB arbiter circuit 2 when there is an access request from the multibus 3 side, and sends a bus permission signal MBEN.
A circuit that puts the multi-port bus 3 in the "WAIT" state until the bus permission signal MBEN returns, opens the gate of the multi-port bus 2 when the bus permission signal MBEN returns, and puts the multi-port bus 3 in the "RDY" state to perform access. It is.

FIG. 6 is a schematic diagram showing state transitions of the MPB arbiter circuit and MB arbiter circuit explained in FIGS. 4 and 5. Therefore, on the board of this embodiment, CPU1 to CPU
3 is installed, and each signal is transmitted and received in the same manner as in each of the above figures.

FIG. 6(a) is a schematic diagram showing the state transition of a four-way access MPB archita circuit, in which 5O1S2. S4. S
6 indicates a no-request state, Sl indicates a CPUI request wait state, S3 indicates a CPU 2 request wait state, S5 indicates a CPU 5 request wait state, and s7 indicates a multibus request wait state. In the figure, if there is no request to the multiport bus, the process goes round and round from SO to S2 to S4 to S6, and when the CPU outputs a bus request, the SO detects it and transitions to St. When the access by CPU 1 ends, the process moves to s2. This action is the CP of each
A bus request is issued to U at the same time and processed sequentially.

FIG. 6(b) is a schematic diagram showing the state transition of the MB Archita circuit, in which So, S6. S7 indicates a no-request state;
For example, Sl indicates a state in which CPU2 in FIG. S4 indicates a state in which the multi-port bus is making a multi-port bus request;
5 indicates a state in which the bus has been used. In the same figure,
When the CPU 2 makes a multibus access request, S
A request is detected at O and the process moves to Sl, preparations are made to acquire the multibus at S2, and the multibus is used via the multiport bus at S3.

If there is an access request for the multiport bus from the multibus, the request is detected in S6, the process moves to S4, and the gate of the multiport bus is opened in S5 to use the multiport bus.

The computer board shown in Fig. 5 is formed by comprehensively incorporating the above, and even when multiple CPUs are installed, the CPUs can be executed in parallel.
Since the memory of the multiport bus can be arranged as a common area, data exchange between the two is possible via this area. It is also possible to arrange the system area on a multi-port bus, eliminating the need for a local bus for each CPU and reducing the number of ICs to be mounted for this purpose.

This example clearly has the following effects.

(+) Realizes CPU parallel processing.

(2) Simplify the data exchange method between CPUs.

(3) Realize resources that can be accessed from multiple directions.

(4) Multiple CPUs can be installed without increasing the number of actual devices C.

(5) It becomes possible to abolish the CPU local bus.

(6) Multiple CPUs can share memory.

H1 Effects of the Invention As stated above, according to the present invention, parallel processing of CPUs is realized, data exchange between CPUs is simplified, resources are realized by access from multiple directions, and the number of actual devices C is increased. It is possible to provide a computer board in which multiple CPUs can share memory by eliminating the local bus without having to do so.

[Brief explanation of drawings]

Figure 1 is a basic configuration diagram of the present invention, Figure 2 is a waveform diagram of the basic configuration, Figure 3 is a configuration diagram of the computer stem, and Figure 4 is a diagram of the basic configuration of the present invention.
The figure is a configuration diagram of an embodiment of the present invention, and FIG. 5 is a CP of the embodiment.
A configuration diagram of the L' boat, FIG. 6 is a schematic diagram of the state transition of the embodiment, and FIG. 7 is a configuration diagram of the coexistence bus interface system.
FIG. 8 is a configuration diagram of a multi-bus/dual port interface system, and FIG. 9 is a waveform diagram of a conventional example. 1.81...CPU port (printed board), 2. . Multiport bus, 3.83...Multibus, II~
13.31. 51-53. 71・CPU, 14
~16,32,33.54~56・Resource, 41~4
3.57-59- CPUn control circuit, 44.
60...MPB arbiter circuit, 45.6■...MB arbiter circuit. Figure 3: General configuration diagram of a computer system Figure 4: Configuration diagram of an embodiment of the present invention Figure 1: Basic configuration diagram of the present invention Figure 2: Waveform diagram of the basic configuration of the present invention Schematic diagram of state transition in the figure example (a) 2RQ

Claims (1)

[Claims] (1) A computer board in which multiple processors and various resources are mounted on a printed board, which is equipped with a multi-port bus connected to a multi-bus outside the printed board, and each processor shares resources via the multi-port bus. A computer board characterized by: