JPS6332649A - Multi-processor system - Google Patents

Abstract

PURPOSE:To decrease the access frequency to a common bus by connecting a common memory and a bus arbiter to a common bus, delivering a permission signal from the bus arbiter to give a reading request to the common memory and holding this request data. CONSTITUTION:When the program reading requests are produced from processor units PU0-n, an access request is sent to a bus arbiter ABT1 via a program reading common bus CBUS1. The arbiter ABT1 controls the access requests given from the units PU0-n and allocates the use of the CBUS1 to these units PU0-n respectively. When the arbiter ABT1 gives permission, the permission signals are given to the units PU0-n. Detecting those permission signals, the units PU0-n transmit the reading request signals and the address information. The data read out of a common memory CM1 are received and transmission of the access requests, reading request and the address information are stopped. Then a program reading action is through.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system, and particularly to a multiprocessor system in which a program storage memory is shared.

[Prior Art] Conventionally, in this type of multiprocessor system,
Each processor unit had its own program storage memory.

[Problems to be Solved by the Invention] In the conventional multiprocessor system described above, each processor unit is provided with a dedicated program storage memory, which has the disadvantage that the total amount of program storage memory becomes large. Another problem was that it was difficult to rewrite the program for each processor unit.

Means for Solving Problem E] To this end, in a multiprocessor system having a plurality of processors, the present invention connects the processor units through a common bus, and connects the common memory and the common bus to the common bus. A bus arbiter that allocates the use of a bus to the processor unit is connected to the processor unit, and the processor unit detects a program read request from the CPU of the processor unit and issues an access request to the bus arbiter, and also detects a permission signal from the bus arbiter. The present invention attempts to solve the above-mentioned problems by adopting a structure including a control means for requesting the common memory to read the data, and a data holding means for holding the data read from the common memory.

[Example] Next, the present invention will be specifically described with reference to the accompanying drawings.

FIG. 1 is a block diagram showing an embodiment of a multiprocessor system according to the present invention. PUO to Pun are processor units, CBUSO is a common bus for data transfer, CBUS 1 is a common bus for program reading, ABTO and ABTI are bus arbiters, CMO
and CMI are common memories. Processor unit PU
O to Pun are connected to a common memory CMO and a bus arbiter ABTO by a common bus CBUSO for data transfer, and to a common memory CMI and a bus arbiter ABTI by a common bus CBUSI for program reading.

When a program read request occurs in each processor unit PUO to Pun, the program read common bus CBU
Sends an access request to bus arbiter ABTI via SI. The bus arbiter ABTI manages access requests from each of the processor units PUO-PUn and performs a process of allocating use of the program reading common bus CBUSI to each of the processor units PUO-PUn.

Since the functions and operations of the bus arbiter ABTI are well known, a detailed explanation thereof will be omitted. Bus arbiter ABT
When I grants permission to the access request, a permission signal is sent to the processor units PUO-Pun via the program reading common bus CBUSI. On the processor units PUO-PUn side, when this permission signal is detected, the common memory CM is sent via the program reading common bus CBUSI.
In order to read the program from I, a read request signal and address information are sent. Also, data from the common memory CMI (
When the program (program) is read out, it is received via the program reading common bus CBUSI, and the sending of the access request, read request signal, and address information is stopped to complete the program reading operation. Successive data write operations using the common memory CMI are performed in the same manner.

FIG. 2 is a block diagram showing the internal configuration of processor units PUO-Pun. For convenience of explanation, only the processor unit Pun will be described, but the other processor units have the same configuration and function. CPU
is the processor, LM is the local memory, IFO, IFI
is an interface circuit, and I Bus is an internal bus.

The processor CPU is connected to the local memory LM and interface circuits IFO and IFI via an internal bus IBUS, and performs internal operations. Also an interface circuit IFO.

IFI is connected to a common bus CBUSO for data transfer and a common bus CBUSI for program reading, respectively.
Accesses common memories CMO and CMI.

FIG. 3 is a block diagram showing an outline of the internal circuit of the interface circuit IFI. BUF is a data holding buffer circuit as data holding means, and CNT is a control circuit as control means. Data retention buffer circuit BUF
are connected to the program reading common bus CBUSI, the internal bus IBUS, and the respective data buses DB, and are controlled by control signals from the control circuit CNT, that is, the gate signal GT and the latch signal LAT. Control circuit CNT
is connected to the address bus AB and control bus CB on the internal bus IBUS side, and monitors the address signal AD, waiting signal WAIT, and read request signal RD. In addition, the control circuit CNT uses a common bus CBUS for program reading.
It is connected to the address bus AB and control bus CB on the I side, and monitors the address signal AD, read request signal RD, access request signal BUSR, and permission signal BUSA.

When a program read request is issued from the processor CPU, the interface circuit IFI detects this. This detection is performed by monitoring address bus AB and read request signal RD by control circuit CNT. That is, it is determined whether the address information at the time when the read request signal RD is detected is within the address range for program storage.

When the control circuit CNT detects a program read request,
A waiting signal WAIT is sent to the internal bus I BUS side to put the processor CPU in a waiting state, and at the same time the common bus C
An access request signal BUSR is sent to the BUSI side to notify the bus arbiter ABTI of the access request. The bus arbiter ABT1 returns the permission signal qBUsA after adjusting bus use requests with other processor units.
Control circuit CNT detects this, relays address signal AD and read request signal RD from internal bus I Bus, and sends them to common bus CBUSI. Data (program) corresponding to the address signal AD and read request signal RD is returned from the common memory CM1 to the data bus DB, and is received by the data holding buffer circuit BUF. At this time, the control circuit CNT sends out the latch signal LAT and the gate signal GT at appropriate timing. Therefore, the data holding buffer circuit BUF holds the data received from the data bus DB on the common bus CBUSI side using the latch signal LAT, and sends it to the data bus DB on the internal bus I BUS side using the gate signal GT. At the same time, the sending of the read request signal RD and the access request signal BUSR to the common bus CBUSi is stopped, and the common bus CBU
Release SI and common memory CMI. Furthermore, the sending of the waiting signal WAIT on the internal bus IBUS side is also stopped, causing the processor CPU to perform a program reading operation. When the reading by the processor CPU is completed and the read request signal RD on the internal bus IBUS side disappears, the control circuit CNT returns to its original state.

[Effects of the Invention] As is clear from the above, the present invention connects the Eki processor units through a common bus in a multiprocessor system having a plurality of processor units, and connects the common memory and the navigation common bus to the common bus. a bus arbiter that allocates usage to the processor unit;
control means that detects a program read request from the bus arbiter and requests access to the bus arbiter, and also detects a permission signal from the bus arbiter and requests the common memory to read the data; and a data holding unit that holds data read from the common memory. Since the present invention is equipped with means, it is possible to reduce the number of accesses to the common bus, shorten the access time, and store the program on the common memory, thereby reducing the amount of memory and making it possible to easily rewrite the program. This has the effect of making it possible to easily change the allocation of processing to each processor unit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the multiprocessor system of the present invention, FIG. 2 is a detailed block diagram of the same part, and FIG. 3 is a detailed block diagram of the same part. puo~Pun: Processor unit CBUSO, CBUSI: Common bus ABTO, ABTI: Bus arbiter CMO, CM1: Common memory CPU: Processor I Bus: Internal bus IFO, IFI: To interface circuit B near address bus DB: Data bus RD: Read request Signal BUF: Data holding buffer circuit CNT: Control circuit GT: Gate signal LAT: Latch signal BUSR: Access request BU, SA: Permission signal CB: Control bus

Claims (1)

[Scope of Claims] In a multiprocessor system having a plurality of processor units, the processor units are connected by a common bus, and a bus arbiter that allocates use of a common memory and the common bus to the processor units is connected to the common bus. and the processor unit has a C of the processor unit.
control means that detects a program read request from a PU and requests access to the bus arbiter, detects a permission signal from the bus arbiter and requests read to the common memory; and data that holds data read from the common memory. A multiprocessor system comprising a holding means.