JP3038257B2 - Electronic computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor electronic computer.

[0002]

2. Description of the Related Art Conventionally, in a multiprocessor computer, when the same processor issues an access request to only one main storage device, a plurality of processors cannot simultaneously access one main storage device. However, there is a problem that the access waiting time of each processor is long and the operation rate of the main storage device is low.

In order to allow the same processor to access a plurality of main storage devices at the same time among a plurality of processors, the following reasons are required under complicated control.
Or it could only be realized with a huge amount of hardware.

I) When only one access request to the main storage device can be issued from the same processor, the waiting time of the processor increases and the use efficiency of the main storage device decreases.

For example, if a plurality of processors need to access a plurality of main storage devices, but a single main storage device (this is supposed to be M0) can access only one at a time, If a processor that wants to access this main storage device M0 (this is now assumed to be A0) has already issued an access request to another main storage device, it waits until all the previous access requests have been processed. Otherwise, an access request to the main storage device M0 cannot be issued. In addition, if another processor issues an access request to the main memory M0 during this waiting time, then the processor A0 sends the main memory M0 until the access request of the other processor is processed. M0
The request for access to is waited for. Thus,
Useless waiting time occurs in the processor A0, and although there is a free time in which the main storage device M0 can also be accessed, a time occurs in which the processor A0 is not accessed by any of the processors, resulting in poor utilization efficiency.

Ii) Any one of the plurality of processors can issue an access request to a plurality of main storage devices. However, when each processor does not have a buffer memory, a plurality of main storage devices are simultaneously stored in one processor. Data may be sent from the device, and at this time, data collision occurs, and data from any main storage device cannot be received. Therefore, priority control is performed. In many cases, the number of main storage devices is proportional to the number of processors, and the number of cases that need to be compared is (number of processors)! / ((The number of processors-the number of main storage devices)!) 〓 (the number of processors)! Therefore, if the number of processors increases, it becomes difficult to perform processing within a prescribed time (clock cycle of the processor).

For example, 1) In the case of two processors and two main storage devices, a maximum of 2! = 2 2) In the case of 4 processors and 4 main storage devices, a maximum of 4! = 24 3) In the case of 8 processors and 8 main storage devices, a maximum of 8! = 40,320 4) In the case of 16 processors and 16 main storage devices, a maximum of 16! = 2.09 × 10 ＾ 13, and the number of cases explosively increases as the configuration increases.

[0008] Further, even when the number of processors and the number of main storage devices are not the same, 5) a maximum of 4! In the case of four processors and two main storage devices. / ((4-2)!) = 12 6) In the case of 8 processors and 4 main storage devices, a maximum of 8! / ((8-4)!) = 1,680 7) In the case of 16 processors and 8 main storages, a maximum of 16! / ((16−8)!) = 518,913,400, which inevitably results in a huge number of cases.

Iii) When a buffer memory is provided in the control device, it is possible to access a plurality of main storage devices from the same processor, but the number of required buffers is as follows: number of main storage devices × number of processors × data width. × Proportionate to the number of access requests that can be issued simultaneously by the processor. In many cases, the number of main storage devices and the number of access requests that can be issued simultaneously are proportional to the number of processors. Therefore, the required number of buffer memories is proportional to the cube of the number of processors. As the number of processors increases, an enormous amount of buffer memory is required. Further, if some control is not performed, there is a problem that it is not easy to know how many buffer memories are actually enough.

For example, when the data width is constant, 1) When two processors and two main storage devices are used, up to two access requests can be issued, and the number of buffers required at this time is 2 × 2 X2 = 8 sets 2) In the case of 4 processors and 4 main storages, up to 4 access requests can be issued, and the number of buffers required at this time is 4 × 4 × 4 = 64 sets 3) Processor 8 In the case of 8 main storage devices, up to 8 access requests can be issued, and the number of buffers required at this time is 8 × 8 × 8 = 512 sets 4) In the case of 16 processors and 16 main storage devices In
Up to 16 access requests can be issued, and the number of buffers required at this time is 16 × 16 × 16 = 4,096 sets. If the number of processors and the number of main storage devices are not the same, 5) if four processors and two main storage devices are used, up to two access requests can be issued. 4 × 2 × 2 = 16 sets 6) In the case of eight processors and four main storage devices, up to four access requests can be issued, and the required number of buffers at this time is 8 × 4 × 4 = 128 sets 7 In the case of 16 processors and 8 main storage devices, up to 8 access requests can be issued, and the number of buffers required at this time is 16 × 8 × 8 = 1,024 sets. Moreover, these are the minimum required numbers, and how many sets are actually required differs depending on the program or the like.

Iv) If the processor has a data width corresponding to the number of main storage devices, data can be received from a plurality of main storage devices at the same time. However, as the number of main storage devices increases, the interconnection between the control device and the processor is reduced. More and more difficult to achieve. The number of interconnects is proportional to the number of processors in other schemes, whereas in this scheme the number of interconnects is proportional to the square of the number of processors when the number of main storage units is proportional to the number of processors.

For example, when handling 32-bit data inside the processor, the total number of data going from the control device to the processor is: 4 processors, 4 2 × 32 = 512 lines, 8 processors, 8 ＾ 2 × 32 = There are 2,048 16 processors, 16 ＾ 2 × 32 = 8,192, which is difficult to mount.

[0013]

As described above, in the conventional multi-processor computer, in order to reduce the waiting time of the processor, an enormous number of buffer memories are prepared or an enormous number of cases are required. It is necessary to prepare a priority control means for the processor or to prepare an input / output data width of the processor in proportion to the number of main storage devices. In any case, an enormous amount of There was a problem that required hardware.

The present invention has been made in view of such a conventional problem. In an electronic computer having a multiprocessor configuration, access control to a main storage device from each of a plurality of processors is controlled by a priority order. An electronic computer capable of issuing an access request from a processor to a plurality of main storage devices, improving the operation rate of the main storage device, shortening the waiting time of the processor, and reducing the amount of hardware. The purpose is to provide.

[0015]

An electronic computer according to the present invention has a plurality of main storage devices, a plurality of processors for performing arithmetic control processing, and a request for holding an access request from the processors to each of the main storage devices. A buffer and a buffer memory provided in each of the processors, the one holding data read from the main storage device for the processor assigned thereto, and the same processor among the plurality of processors. When the access right of a plurality of main storage devices is obtained, priority control for controlling not to issue an access request from the processor to the main storage device during a cycle corresponding to the number of main storage devices simultaneously accessed. Means and a buffer when the buffer memory of each of the processors holds data from a plurality of main storage devices. In order in which and a data control means for controlling to output the data to the processor in charge of their own.

[0016]

In the computer according to the present invention, a buffer memory is provided in an amount corresponding to the main storage device for each processor, and when the same processor obtains an access right to a plurality of main storage devices, it accesses simultaneously. During a cycle corresponding to the number of main storage devices, a plurality of main storage devices are controlled by priority control means so that the processor does not issue an access request to another main storage device so that each processor does not compete with each other. The device can be accessed simultaneously, the operation rate of the main storage device is improved, and the waiting time of the processor is reduced.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a system configuration according to an embodiment of the present invention, in which a plurality of main storage devices M0, M1, M2,.
And processors A0 and A for performing a plurality of arithmetic control processes
, A2,..., And request buffers C0, C1, C2,.
And buffer memories B0, B1, B2,... Which are provided for each processor and hold data read for each processor from each main storage device.

Also, as a feature of the present invention, when the same processor among the processors A0, A1, A2,... During the cycle, when the priority control device 1 controls the processor so as not to issue an access request to the main storage device, and when the buffer memory of each processor holds data from a plurality of main storage devices. , Which control data to be output to its own processor in a predetermined order.

Next, the operation of the computer having the above configuration will be described.

, Which hold access requests issued to the main storage devices M0, M1, M2,... From the processors A0, A1, A2,. Assigns priorities to these access requests, and accesses each of the main storage devices M0, M1, M2,.

The priority control method is as follows. When a certain processor obtains an access right to n out of a plurality of main storage devices, the immediately following (n-1) cycle During this period, no access request is issued from the request buffer, and in other cases, control is independently performed for each main storage device.

Referring to FIG. 2, the processor A
Assuming that 0, A1, A2, and A3, for example, have issued an access request to the request buffer B0 corresponding to the main storage device M0, at this time, each processor also issues an access request to another main storage device at the same time. be able to. Therefore, the priority control device 1 performs access priority control for each main storage device, and issues one request to each main storage device. Normally, the priority control device 1 does not participate in accessing another main storage device, for example, the main storage device M3. For this reason, the priority control is independently performed on the processor for each main storage device. Then, in a certain cycle, one processor A0 stores a plurality of main storage devices M0, M1, and M2.
When the access right is obtained for one, the access of the processor A0 is prohibited during the immediately following cycle, in this example, for 2 (= 3-1) cycles. During this time, the remaining processors A1, A2, and A3 access the main storage device. Then, after this period, the processor A0 is again added to the priority control.

Data read control in response to an access request to the main storage device that has been subjected to priority control in this way is performed according to the procedure shown in detail in FIG. That is, the data from the main storage device M0 is sent by the first data control device D01 to the buffer memory B0 of the processor A0 that has issued the access request. Here, the first data control device D01 has a configuration such that each main storage device such as a crossbar switch can transmit data independently of other main storage devices.

Therefore, if there is an access request from the same processor to a plurality of main storage devices at the same time, the sections B00, B01, B02, etc. of the buffer memory B0 are almost simultaneously provided as long as the performance of each main storage device is the same. Is read and held. Therefore, at this time, if no control is performed, the processor A
Since the data read from each main storage device is input to 0 and a conflict occurs, the conflict is avoided by data control by another second data control device D02.

The data control method by the second data control device D02 is used when the main storage device M0 does not compete with the other main storage devices M1 to M3 with respect to the data read by the access request from the processor A0. Inputs data to the processor A0 through the buffer memory B0 and through the second data controller D02. However, when a conflict occurs, the second data control device D02 transmits only one of the conflicting data through the buffer memory B0 and the processor A0 through the second data control device D02.
And other conflicting data is temporarily stored in a corresponding section of the sections B00, B01, B02, and B03 of the buffer memory B0, and is sequentially stored in the buffer after the processor A0 completes processing of the previously input data. Control is performed so as to be input from the memory B0 to the processor A0.

In this case, a certain processor is controlled by the priority control device 1 so that a certain one of the plurality of main storage devices
When the access right is obtained for the table, (n-
1) During the cycle, no access request is issued from the request buffer. In other cases, priority control is performed so that control is performed independently for each main storage device. No new data is sent to the buffer memory B0 until all data has been sent to the processor A0. Therefore, it is sufficient that each buffer memory B0, B1, B2,.

As described above, in the computer according to this embodiment, when one processor simultaneously requests access to a plurality of main storage devices, priority control is performed independently for each main storage device. Since the number of processes in each main storage device is proportional to the number of processors, the total number of processes is at most equal to the number of processors × the number of storage devices, and the process can be performed in proportion to the square of the processors. .

For example, 1) a maximum of 2 × 2 = 4 in the case of two processors and two main storages 2) a maximum of 4 × 4 = 163 in the case of four processors and four main storages 4) In the case of 8 processors and 8 main storage devices, the maximum is 8 × 8 = 64. 4) In the case of 16 processors and 16 main storage devices, the maximum is 16 × 16 = 256. Further, even when the number of processors and the number of main storage devices are not the same, 5) in the case of 4 processors and 2 main storage devices, a maximum of 4 × 2 = 8 6) 8 processors and 4 main storage devices In the case of a unit, the maximum is 8 × 4 = 32 7) 16 processors, and in the case of eight main storages, the maximum is 16 × 8 = 128.

Therefore, when this is compared with a conventional case without a buffer memory, when the number of processors exceeds 8, the number of cases to be compared is greatly reduced.

Further, since it is sufficient that the number of buffer memories is equal to the number of main storage devices for each processor, it is sufficient to have the number of processors × the number of main storage devices, and it is sufficient to have the number proportional to the square of the processors.

For example, when the data width is constant, 1) the number of buffers required for 2 processors and 2 main storage devices is 2 × 2 = 4 sets 2) 4 processors and main storage device 4 The number of buffers required in the case of 4 is 4 × 4 = 16 sets 3) The number of buffers required in the case of 8 processors and 8 main storage units is 8 × 8 = 64 sets 4) 16 processors, main storage The number of buffers required for 16 devices is 16 × 16 = 254 sets. If the number of processors and the number of main storage devices are not the same, 5) the number of buffers required for 4 processors and 2 main storage devices is 4 × 2 = 8 sets. 6) 8 processors, The number of buffers required for four storage devices is 8 × 4 = 32 sets. 7) The number of buffers required for 16 processors and eight main storage devices is 16 × 8 = 128 sets. At the same time, these numbers are also sufficient to provide priority control.

Comparing this with the conventional case where priority control is not performed, it can be seen that when the number of processors exceeds four, the number of buffer memories is greatly reduced.

Further, a processor which has issued an access request to a plurality of main storage devices, while being unable to issue an access request,
Since the period for receiving data from the buffer memory is set, unnecessary waiting time of each processor does not occur. In addition, during the period in which the access request is invalidated, the processing can be performed one clock later than in the case where the conventional buffer memory is not provided, so that the processing becomes easier and the number of connectable processors can be increased.

The present invention is not limited to the above embodiment, and the number of processors and the number of main storage devices can be increased or decreased.

[0036]

As described above, according to the present invention, in a multiprocessor computer, when each processor accesses the same main storage device at the same time, priority control is performed. Enables simultaneous access of multiple main memory runs from one processor with a small amount of hardware, shortens the waiting time of the processor,
The operation rate of the main storage device can be improved.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram of an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an access request operation of the embodiment.

FIG. 3 is an explanatory diagram showing a data read operation of the embodiment.

[Explanation of symbols]

M0, M1, M2,... Main storage device A0, A1, A2,... Processor B0, B1, B2,. , B21, B22, B23,... Memory sections B30, B31, B32, B33,... Memory sections C0, C1, C2,..., Request buffers D0, D1, D2, ..., Data controllers D01, D11, D21,. Control device D02, D12, D22, ... second data control device

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G06F 12/00-12/06 G06F 15/16-15/177

Claims (1)

(57) [Claims] 1. A plurality of main storage devices, a plurality of processors for performing arithmetic control processing, a request buffer for holding an access request from the processors to each of the main storage devices, and a buffer memory for each of the processors And
The one that holds data read for the processor that is responsible for itself from each of the main storage devices; and the one that is simultaneously accessed when the same processor among the plurality of processors has an access right to a plurality of main storage devices. Priority control means for controlling not to issue an access request from the processor to the main storage device during a cycle corresponding to the number of main storage devices to be executed; and A data control means for controlling to output the data to its own processor in a predetermined order when the data is held.