JPS61182158A - Common bus occupying system - Google Patents

Abstract

PURPOSE:To occupy the priority by selecting the bus of the high level of a common bus occupying priority rank level and selecting the same level bus by the method stipulated for a level each, when a common bus occupancy is requested from plural function modules. CONSTITUTION:When a bus occupancy requesting signal is outputted from a channel 6 and a processor 2, at a bus occupying control circuit 1, bus occupying request signals REQ1-1, and REQ2-1 are 'in' and detected. When the REQ1-1 and 2-1 are on, counters 1-1 and 2-1 corresponding to this start to count a clock CL. Comparators 1-2 and 2-1 respectively receive the counted value of the counters 1-1 and 2-1. At such a time, the comparator 1-1 compares with other counter in the group of the level 1, namely, other counted value output (c) outputted from the counter 1-2, etc., when the counted value is the largest, a bus occupying permitting signal GNT1-1 is sent to a channel 6. At such a time, the function of the comparator 2-1 belonging to the level 2 group is stopped by the stopping signal sent from an OR circuit 17.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing system that uses a common bus as a signal line for carrying data, and particularly to a common bus occupancy method that effectively utilizes the data transfer capability of the common bus.

Methods for transferring data between multiple functional modules (e.g., a processor, one channel of memory, etc.) connected to a data processing system can be roughly divided into methods that transfer data through signal lines corresponding to the functional modules (e.g.,
There are a star connection method) and a method of time-divisionally transferring data using a common IMi signal line (for example, a common bus connection method).

Although the two methods (star connection method and common bus connection method) have their own advantages and disadvantages, the common bus connection method is more commonly used in the TL'iE data processing system.

It is expected that a control system that more effectively utilizes the data transfer capability of such a common bus connection system will be put into practical use.

[Prior art and problems to be solved by the invention] FIG. 3 shows a common bus connection system diagram, and FIG. 4 shows a block diagram of a conventional common bus occupancy control circuit.

In the common bus connection system shown in FIG. 3, data is transferred between the processor 2, 3, memories 4 and 5, and channels 6 to 9 connected to the common bus connection system, for example, from memory 4 to channel 6. If desired, a request signal to occupy the common bus a is output from the memory 4 to the bus occupancy control circuit 1.

Based on this lotus occupancy request signal, the lotus occupancy control circuit 1 outputs an occupancy permission signal to the memory 4, so that the lotus occupancy control circuit l outputs an occupancy permission signal to the memory 4, thereby allowing the lotus occupancy to be checked from the memory 4 via the common bus a. Data transfer is performed for 2 and 6.

Conventional common bus occupancy control using such a method can be broadly classified into the following two control methods. That is, (1) each functional module (processor 2, 3, memory 4, 5, channels 6 to 9) connected to common bus a
etc.), and when a conflict occurs between bus occupancy request signals, the bus occupancy right is acquired in order of priority.

In this method, for example, channels 6, etc., which are connected to devices with severe time constraints, such as the magnetic disk device 68, are given a high priority, and their control circuit has a configuration example as shown in Fig. 4. That is, the bus occupancy right has the highest priority for the bus occupancy request signal REQL, followed by the bus occupancy request signals REQ2 and REQ3.

For example, when the bus occupancy request signals REold and REQ2 conflict, the bus occupancy permission signal GNTI is first issued, and after the data transfer is completed, the bus occupancy permission signal GNT2 is issued.

(2). The other method is a method in which there is no priority setting among the functional modules connected to the common bus a, and the right to occupy the lot is acquired from the one with the longest waiting time.

Since both conventional methods process based on one fixed method, for example, if there is a lotus occupancy request signal from something with strict time constraints, it will be processed with priority, or if there is a conflict when the priority level seems to be the same. However, there is a problem in that it is not possible to obtain bus occupancy with flexibility depending on the content of data processing, such as processing data with the longest waiting time first.

[Means for solving problems]

The present invention aims to realize a new common bus occupancy method that solves the above-mentioned problems. , a control means for controlling common bus occupancy requests from the functional modules is provided, and when the common bus occupancy requests are made from a plurality of functional modules, the one with a higher common bus occupancy priority level (I occupies the first and the same The common bus occupancy system according to the present invention, which prioritizes occupancy according to a method determined for each level, solves the problem.

[Effect]

That is, the common bus occupancy priority is divided into multiple levels,
Each functional module selects one of the plurality of levels and issues a common bus occupancy request. At this time, conflicts between functional module groups with different common bus occupancy priority levels are handled with priority to those with higher priority levels, and conflicts between function modules with the same common bus occupancy priority level are handled in advance at that level. By prioritizing processing using this method, necessary processing can be performed at the necessary timing, and the limited common bus transfer capacity can be used effectively.

As for the common bus transfer capacity, for example, if one second is taken as one processing unit, and one lotus processing time is divided into, for example, 1/8 based on the data processing time, the transfer capacity of this bus is eight processing capacities. It is called.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 1 and 2.

FIG. 1 shows an embodiment of a common bus occupancy control circuit according to the present invention, and FIG. 2 shows a common bus occupancy control sequence diagram according to the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

Next, an operational diagram of this embodiment will be explained. It is assumed that the transfer capacity of the common bus a in this embodiment is, for example, 8 processing capacity per second.

In this embodiment, the occupation priority level of the common bus a of each functional module (processors 2, 3, memories 4, 5, channels 6 to 9, etc.) connected to the common bus connection system shown in FIG. 3 is set to 2. Assume that it is divided into two levels.

Furthermore, in this embodiment, among the processing methods for the same level, priority processing is given to the one with the longest waiting time. That is, at the timing when the magnetic disk devices 6a, 7a,
Channels 6 to 8, which control the Cm tape device 88, etc., use level ■, and channel 9, which controls the processors 2 and 3, memories 4 and 5, and display device 9a, uses level ■, Furthermore, it is assumed that level ■ has a higher priority than level ■.

In such a state, for example, when a bus occupancy request signal is output from the channel 6 and the processor 2, the bus occupancy control circuit 1 outputs the bus occupancy request signal REQ1-1, rlEQ.
Detection is made when 2-1 turns on. Lotus occupancy control circuit R
When EQI-, 1 and REQ2-1 are turned on, the corresponding counter 1-1 and counter 2.1 start counting using the bus clock CL.

Also, comparator 1-1 and comparator 2-1 are counter 1. ．． 1 and the count values of counter 2-1 are received.

At this time, the comparator 1-1 outputs a bus occupancy permission signal GNTI when the count value is the largest compared to other count value outputs C output from other counters in the group, that is, counters 1-2, etc. -1 to channel 6. Incidentally, the count value output indicates a lead sent to other comparators 1-2, etc. at the same level.

Also, when channel 6 receives bus occupancy permission signal GNTI-1, it issues bus occupancy request signal I? Since E old-1 is turned off, the count of counter 1-1 does not advance. Furthermore, the counter 1-1 is cleared by the bus occupancy permission signal GNTI-1. In addition, comparator 2-1 belonging to the level ■ group
is the suppression signal sup■ sent from the OR circuit 17
Is the bus occupation request signal 1? [The function is stopped while EQl-1 is on.

Next, if the signal 12E port 1-1 is turned off and there is no bus occupation request from the level ■ group, the comparator 2-1 is turned off.
1 compares the count value of the counter 2-1 that counts the request signal RE port 2-1 from the processor 2 with the count value output C of other counters 2-2, etc. in the level ■ group, and calculates the count value of the counter 2-1. If the count value of 1 is the longest, the bus occupancy permission signal GN
T2-1 is sent to processor 2.

Note that the processing of the counter 2-1 is similar to that of the counter 1-1 described above, in which counting is stopped, cleared, and the counter waits for the next activation.

Next, for example, bus occupancy request signals REQI-1 to REQI-3 from channels 6 to 8 of the level ■ group, and bus occupancy request signals REQ2-1 to REQ2-1 to from the processors 2 and 3 and memory 4.5 of the level ■ group. If REQ2-4 are output, first the signals REQI-1 to REQI-3 are output.
In the order of the longest waiting time, that is, in the order of the waiting time in FIG.
), one unit time of common bus a (of the eight slots (b) of al, first channel 6, then channel 7, and then channel 8 occupy common bus a, and data transfer.

Note that (1) in FIG. 2 indicates a bus occupancy module, and (2) indicates a level 1 path occupancy request signal RE ports 1-1 to R.
EQI-3, (3) is the level 2 bus occupancy request signal RE
Q2-1 to REQ2-4, (4) are level 1 bus occupancy permission signals GNTI-1 to GNTI-3, and (5) are level 2 bus occupancy permission signals GNT2-1 to GNT2-4 on (in the figure). The solid line indicates on).

Next, if there are no signals REQI-1 to REQI-3 from the level ■ group when the level ■ group ends, the processor 3 is moved to the fifth slot (
Signal 1111E again from channel 6 during processing in b)
When QI-1 is output, channel 6 is processed with priority in the sixth slot (b).

Furthermore, if there is no bus occupancy request from the level group at this point, memory 4 will be processed in the 7th slot, tbl, and if an occupancy request RE old 2 is generated from channel 7, the 7th slot will be processed. Channel 7 is processed in h(bl), and processing in memory 5 is made to wait until the next time (a).

In this way, the lotus transfer ability is dynamically accommodated between levels,
Controlled to maximize bus transfer capacity.

〔Effect of the invention〕

According to the present invention as described above, the number of connectable functional modules can be increased by effectively utilizing the lotus transfer capability, and the flexibility of the system can be improved.

[Brief explanation of the drawing]

Fig. 1 is a diagram of an embodiment of the common bus occupancy control circuit according to the present invention, Fig. 2 is a common bus occupancy control sequence diagram according to the present invention, Fig. 3 is a common bus connection system diagram, and Fig. 4 is a conventional common bus occupancy control. The block diagrams of the circuits are shown respectively. In the figure, 1 is a bus occupancy control circuit, 2.3 is a processor, 4.5 is a memory, 6 to 9 are channels, 6a and 7a are magnetic disk devices, 8a is a magnetic tape device, 9a is a display device, 1
0.11 is an AND circuit, 12a and 12b are inverters, 13a, 13b, 15a, and 15b are counters, 14a, 14b, 16a, and 16b are comparators, and 17 is an OR circuit, respectively. Part 1 Illustration 3 Figure 4 Figure 4

Claims (1)

[Claims] In a data processing system having a large number of functional modules and transferring data between arbitrary functional modules via a common bus, a priority level designating means for designating a priority level at which the functional module occupies the common bus; is provided with a control means for controlling the common bus occupancy request of a plurality of functional modules, and when there is a common bus occupancy request from a plurality of functional modules, a module having a higher level of the common bus occupancy priority level takes priority occupancy,
A common bus occupancy system characterized by priority occupancy of devices at the same level according to a method determined for each level.