JP2002351821A - Mediation control method and circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a mediation control circuit which achieves simplification and speeding up of a circuit by performing both the selection of demandant candidates based on a mediation algorithm and the final selection of demandant based on a round robin in a lump. SOLUTION: This circuit is provided with a latch circuit 11 which latches N bits of mediation results, a plurality of first arithmetic circuits 40 to 40n which output comparative figure data for round robin by performing respective different unsigned integer operations to the previous mediation results outputted from the latch circuit 11, a comparator 31 which outputs a maximum value in comparison of unsigned integers in unit of M+N bits consisting of N bits output from the first arithmetic circuit 40 to 40n as low- bits and M bits of comparative figure data presented by each demandant for the mediation algorithm as high- bits, and a second arithmetic circuit 21 which inputs the subtraction results obtained by unsigned subtracting the value shown in the low order N bits of the output of the comparator 31 from the output of the latch circuit 11 as the mediation result of this time to the above latch circuit 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arbitration control circuit used for arbitration of a switching device, a bus access, and the like, and more particularly, to a case where there are a plurality of request sources that should be treated basically equally. In particular, when the arbitration algorithm takes a procedure of selecting the maximum value or the minimum value from the data values presented by each request source and selecting the request source presenting the value as a selection result, the arbitration algorithm corresponds to the maximum value or the minimum value. The present invention relates to an arbitration control method and circuit for applying a round robin (rotation priority) control to finally determine one request source when a value is presented from a plurality of request sources.

[0002]

2. Description of the Related Art The round robin method used for arbitration of switching devices and bus access has a long history, and many realization methods have been proposed. The round-robin method is an arbitration in which a request source that is to be treated basically equally is given a right to fairly access a shared resource such as a shared band or a bus.

[0003] Japanese Patent Application Laid-Open No. H11-219335 discloses a conventional technique for this type of round robin. In this prior art, a bit sequence of a request signal of 1 bit indicating presence / absence of a request and a search signal in which only one bit is 1 are searched for a bit sequence of the request signal from a bit position where the search signal is 1. A round-robin scan in which a permission signal corresponding to a bit whose request signal is 1 is initially set to 1 and a permission signal corresponding to other bits is set to 0 can be realized by a combinational logic circuit such as an addition circuit or a logic circuit. Since the round robin result can be uniquely obtained only by the combinational logic circuit, high-speed processing is possible.

In this prior art, a 1-bit flag indicating either 0 or 1 can be used as a search factor (request signal), and it is possible to process them in several stages. is there. However, in this conventional technique, when the arbitration algorithm selects a request source by comparing numerical values consisting of a plurality of bits calculated from various factors, after all, a circuit for comparison is prepared at the preceding stage, and as a result, Must be flagged again and input to the round robin control circuit. As described above, in the conventional technique, when the data presented by the request source is a plurality of bits, two or more stages of processing are required until an arbitration result is output, which increases the circuit scale and the processing speed. There is another problem that cannot be improved.

On the other hand, as a prior art for simultaneously performing an arbitration algorithm and comparison by round robin, Japanese Patent Laid-Open No. 1-2
No. 96365. In this prior art, a counter is provided for each of a plurality of interface devices that access a common bus, and each interface device outputs a counter value,
Each interface device compares its own output counter value with the maximum value of the counter values output from all devices to determine a match or mismatch, and the matched interface device acquires the bus use right and the bus use right. It is shown that all interface devices having a counter value smaller than the counter value of the device that has acquired the counter count up the counter, and the interface device that has acquired the right to use the bus sets the counter to the minimum value.

The problem with this prior art is that the comparison value (counter value) must first be different for each request source (each interface device) as a necessary condition for comparison.

Further, in this prior art, priority information is added to the most significant bit of the counter value and output.
Although it is disclosed that the comparison is performed, in this conventional technique, in order to output the arbitration results collectively, all the priority information is different for each request source similarly to the original arbitration comparison value (counter value). Must be able to output values. If the values to be added to the upper bits are not all different for each requester, two counters are prepared for each interface device as shown in this prior art, and the upper bits (first Two steps in which only the request source permitted to participate in the second comparison outputs the contents of the second counter to the arbitration bus. It is necessary to take the following steps.

In this prior art, a first counter and a second counter are used.
Are connected to a common bus. However, it is assumed that the buses of the respective counters are separated, and the values of the first counter and the second counter are simultaneously transmitted by the respective interface devices. For example, there is a request source A in which the first counter has the maximum value and the second counter has the second value, and a request source B in which the first counter has the second value and the second counter has the maximum value. At this time, in the request source A, the comparison result based on the output of the first counter indicates the maximum value, but the comparison result based on the output of the second counter does not indicate that it is the maximum value. As described above, according to this conventional technique, when the outputs of the two counters are output at the same time, it is impossible to determine whether or not the self should be selected. That is, in this prior art, the request source B
Recognizes from the result of the first counter that he has dropped out in the selection stage of the first counter, and withdraws the output of the second counter for the first time.
Can be recognized that the comparison result in the second counter is the maximum.

In the end, the request source selection based on the specific factor corresponding to the first stage is performed first, and when a plurality of request sources are arranged at the same time, the next second stage re-determines a unique address. This is not particularly different from the former conventional technique using an arbitration circuit that can perform the arbitration.

[0010]

As described above, in the prior art, when arbitration is performed by comparing calculated values due to factors specific to the arbitration algorithm, a round robin at that time, that is, a final unique selection is performed. The procedures are inevitably separated, requiring two or more steps.
For this reason, in the related art, the circuit configuration is difficult to understand and becomes complicated and large-scale. In addition, the number of clock steps increases, high-speed processing cannot be performed, and a system that needs to perform arbitration at high speed becomes a speed bottleneck.

[0011] The present invention has been made in view of the above,
It is an object of the present invention to obtain an arbitration control circuit that realizes simplification and high-speed circuit by collectively performing selection of request source candidates by an arbitration algorithm and final request source selection by round robin.

[0012]

To achieve the above object, an arbitration control method according to the present invention selects a maximum value or a minimum value from data values presented by a plurality of request sources, and selects the maximum value or the minimum value. Is applied to the arbitration algorithm that selects the requesting source presenting the value, and when a value corresponding to the maximum value or the minimum value is presented from a plurality of requesting sources,
In the arbitration control method using round robin control to finally determine one request source, the upper M bits are used as first comparative numerical data presented by each request source for the arbitration algorithm, and the lower N bits are used in the previous Arbitration results are subjected to different predetermined calculations for each request source.
A second comparison numerical data for round robin composed of an integer value of bits is obtained, and the first and second comparison numerical data of a plurality of request sources are compared as an M + N-bit unsigned integer. The present arbitration result is obtained based on searching for a maximum value or a minimum value of data.

According to the present invention, the upper M bits are used as the first comparison numerical data presented by each requester for the arbitration algorithm, and the lower N bits are used in the previous arbitration result and are different from each other for each request source. Are performed, and the second and fourth comparison numerical data for a plurality of request sources are M + N-bit unsigned integers. The arbitration result of this time is obtained based on searching for the maximum value or the minimum value of the M + N-bit data by comparing. That is, by comparing the first and second comparison numerical data for a plurality of request sources as unsigned integers of M + N bits, a request source is selected by an arbitration algorithm for upper M bits and a request source is uniquely selected by lower N bits. And are executed collectively in one step.

The arbitration control circuit according to the next invention is applied to an arbitration algorithm that selects a maximum value from data values presented by a plurality of request sources and selects a request source presenting the maximum value as a selection result. In a case where a value corresponding to the maximum value is presented from a plurality of request sources, an arbitration control circuit using round robin control to finally determine one request source, arbitration of N bits using a clock signal as a trigger A latch circuit for latching a result, and a plurality of units each performing a different unsigned integer operation on the previous arbitration result output from the latch circuit and outputting round-robin comparative numerical data composed of all N-bit integer values. And the N-bit output from each of these first arithmetic circuits as lower bits, and the M-bits presented by each request source for the arbitration algorithm. A comparator that outputs the maximum value by comparing the combined data of a plurality of request sources obtained by combining the comparison value data as the upper bits as unsigned integers of M + N bits, and that the lower N bits of the output of the comparator are A second arithmetic circuit that subtracts an unsigned value from the previous arbitration result output from the latch circuit, and inputs the subtraction result to the latch circuit as a current arbitration result,
An arbitration algorithm for searching for the maximum value and round robin are collectively executed in one clock cycle to derive only one arbitration result.

According to the present invention, the plurality of first arithmetic circuits perform different unsigned integer arithmetic operations on the previous arbitration results output from the latch circuits, respectively, and perform round robins each having a different integer value of N bits. Output comparative numerical data for The comparator uses the N-bit output from each of the first arithmetic circuits as lower bits, and combines the M-bit comparison numerical data presented by each requester for the arbitration algorithm as upper bits, for a plurality of request sources. The combined data is compared as an M + N-bit unsigned integer and the maximum value is output. The second arithmetic circuit subtracts, without sign, the value indicated by the lower N bits of the output of the comparator from the previous arbitration result output from the latch circuit, and uses the subtraction result as the current arbitration result. Input to the circuit. In this way, an arbitration algorithm for searching for the maximum value and round robin are collectively executed in one clock cycle to derive only one arbitration result.

In the arbitration control circuit according to the next invention, when n = 2 ^N -1 and L is an integer from 0 to n in the above invention, each of the first arithmetic circuits includes By adding (n-L + 1) to the output, L
The method is characterized in that round-robin comparison numerical data corresponding to the th requester is output.

According to the present invention, the first arithmetic circuit adds (n−L + 1) to the output of the latch circuit to output round-robin comparison numerical data corresponding to the L-th request source. .

The arbitration control circuit according to the next invention is the arbitration control circuit according to the above invention, wherein a flag signal indicating the presence / absence of a request from each requester is inputted to the comparator as the most significant bit, and the most significant bit output of the comparator is outputted to the comparator. It is characterized in that it is inputted as an enable signal to a latch circuit.

According to the present invention, a flag signal indicating the presence / absence of a request from each requester is input to the comparator as the most significant bit, and the most significant bit output of the comparator is input to the latch circuit as an enable signal. If no request is issued from all request sources, the arbitration operation is not executed.

The arbitration control circuit according to the next invention is applied to an arbitration algorithm that selects a maximum value from among data values presented by a plurality of request sources and selects a request source presenting the maximum value as a selection result. In a case where a value corresponding to the maximum value is presented from a plurality of request sources, an arbitration control circuit using round robin control to finally determine one request source, arbitration of N bits using a clock signal as a trigger A latch circuit for latching a result, and a plurality of units each performing a different unsigned integer operation on the previous arbitration result output from the latch circuit and outputting round-robin comparative numerical data composed of all N-bit integer values. And the N-bit output from each of these arithmetic circuits as lower bits, and the M-bit comparison numerical data presented by each requester for the arbitration algorithm. Are compared as unsigned integers of M + N bits, and the number of the request source having the maximum value is output by this comparison, and this number data is used as the arbitration result of this time. A comparator to be input to the latch circuit, wherein a single arbitration result is derived by collectively executing an arbitration algorithm for searching for a maximum value and round robin in one clock cycle.

According to the present invention, in the plurality of arithmetic circuits,
Each of the previous arbitration results output from the latch circuit is subjected to a different unsigned integer operation, and round-robin comparison numerical data composed of all different N-bit integer values is output. In the comparator, the N-bit output from each of these arithmetic circuits is used as lower bits, and the M-bit comparison numerical data presented by each requester for the arbitration algorithm is used as upper bits to generate combined data for a plurality of requesters. Number data corresponding to the maximum value is output by comparing as M + N unsigned integers. The output of the comparator, that is, the number data is input to the latch circuit as the result of the current arbitration.

The arbitration control circuit according to the next invention is applied to an arbitration algorithm that selects a minimum value among data values presented by a plurality of request sources and selects a request source presenting the minimum value as a selection result. In a case where a value corresponding to the minimum value is presented from a plurality of request sources, an arbitration control circuit using round robin control to finally determine one request source, arbitration of N bits by using a clock signal as a trigger A latch circuit for latching a result, and a plurality of units each performing a different unsigned integer operation on the previous arbitration result output from the latch circuit and outputting round-robin comparative numerical data composed of all N-bit integer values. And the N-bit output from each of these first arithmetic circuits as lower bits, and the M-bits presented by each request source for the arbitration algorithm. A comparator that outputs the minimum value by comparing the combined data of a plurality of request sources obtained by combining the comparison value data as the upper bits as unsigned integers of M + N bits, and that the lower N bits of the output of the comparator are The result of the present arbitration is obtained based on unsigned addition of the indicated value and the previous arbitration result output from the latch circuit,
A second arithmetic circuit for inputting the current arbitration result to the latch circuit, and arbitration algorithm for searching for the minimum value and round robin are collectively executed in one clock cycle to derive only one arbitration result. It is characterized by the following.

According to the present invention, the plurality of first arithmetic circuits perform different unsigned integer arithmetic operations on the previous arbitration results output from the latch circuits, respectively, and perform round robins each having a different integer value of N bits. Output comparative numerical data for The comparator uses the N-bit output from each of the first arithmetic circuits as lower bits, and combines the M-bit comparison numerical data presented by each requester for the arbitration algorithm as upper bits, for a plurality of request sources. The combined data is compared as an M + N-bit unsigned integer, and the minimum value is output. The second arithmetic circuit obtains the current arbitration result based on the unsigned addition of the value indicated by the lower N bits of the output of the comparator and the previous arbitration result output from the latch circuit. The result of this arbitration is input to the latch circuit. In this way, the arbitration algorithm for searching for the minimum value and round robin are collectively executed in one clock cycle to derive only one arbitration result.

In the arbitration control circuit according to the next invention, in the above invention, when n = 2 ^N -1 and L is an integer from 0 to n, each of the first arithmetic circuits has a value (L +
n) by subtracting the output of the latch circuit from
The second arithmetic circuit outputs round-robin comparison numerical data corresponding to the L-th request source, and the second arithmetic circuit outputs the value indicated by the lower N bits of the output of the comparator and the latch circuit. The present arbitration result is obtained based on the unsigned addition of the previous arbitration result and the value 1.

According to this invention, the first arithmetic circuit subtracts the output of the latch circuit from the value (L + n) to output round-robin comparison numerical data corresponding to the L-th request source. . The second arithmetic circuit adds the value indicated by the lower N bits of the output of the comparator, the previous arbitration result output from the latch circuit, and the value 1 without sign to the current arbitration result. Get.

The arbitration control circuit according to the next invention is the arbitration control circuit according to the above invention, wherein a flag signal indicating whether or not each requester has made a request is input to the comparator as the most significant bit, and the most significant bit output of the comparator is output. Is logically inverted and input to the latch circuit as an enable signal.

According to the present invention, a flag signal indicating the presence / absence of a request from each requester is input to the comparator as the most significant bit, and the output of the most significant bit of the comparator is logically inverted so as to be supplied to the latch circuit as an enable signal. By inputting, the arbitration operation is not executed when no request is issued from all request sources.

The arbitration control circuit according to the next invention is applied to an arbitration algorithm which selects a minimum value from data values presented by a plurality of request sources and selects a request source presenting the minimum value as a selection result. In a case where a value corresponding to the minimum value is presented from a plurality of request sources, an arbitration control circuit using round robin control to finally determine one request source, arbitration of N bits by using a clock signal as a trigger A latch circuit for latching a result, and a plurality of units each performing a different unsigned integer operation on the previous arbitration result output from the latch circuit and outputting round-robin comparative numerical data composed of all N-bit integer values. And the N-bit output from each of these arithmetic circuits as lower bits, and the M-bit comparison numerical data presented by each requester for the arbitration algorithm. Are compared as unsigned integers of M + N bits, and the number of the request source having the minimum value is output by this comparison, and this number data is used as the current arbitration result. A comparator to be input to the latch circuit, wherein a single arbitration result is derived by collectively executing an arbitration algorithm for searching for a minimum value and round robin in one clock cycle.

According to the present invention, in the plurality of arithmetic circuits,
Each of the previous arbitration results output from the latch circuit is subjected to a different unsigned integer operation, and round-robin comparison numerical data composed of all different N-bit integer values is output. In the comparator, the N-bit output from each of these arithmetic circuits is used as lower bits, and the M-bit comparison numerical data presented by each requester for the arbitration algorithm is used as upper bits to generate combined data for a plurality of requesters. The data is compared as M + N unsigned integers and number data corresponding to the minimum value is output. The output of the comparator, that is, the number data is input to the latch circuit as the result of the current arbitration.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of an arbitration control circuit according to the present invention will be described below in detail with reference to the accompanying drawings.

Embodiment 1 Embodiment 1 of the present invention will be described with reference to FIGS. In Embodiment 1, the arbitration algorithm implements a round robin function in the case of selecting the one that outputs the maximum value among the numerical values presented by the request source. FIG. 1 is a diagram that is extracted and shown only for a portion particularly related to round robin.

In FIG. 1, an N-bit DFF (latch circuit, D-type flip-flop circuit) 11 latches a round robin result (N bits) indicating a selected request source with a clock signal as a trigger. Things. The arithmetic circuit 21 subtracts the output b (N bits) of the comparator 31 by an unsigned integer from the previous round robin result a (N bits) held by the DFF 11, and calculates the subtraction result (ab). Output to DFF11.

Each of the arithmetic circuits 40 to 4n (n = 2 ^N -1) performs the operation shown in the frame on the input output value of the DFF 11, that is, the previous round robin result a (N bits), and Output the comparison numerical value for For example, the arithmetic circuit 40 corresponds to the request source “0”,
An N-bit unsigned addition of +0 to the output value (N bits) of the DFF 11 is performed. The arithmetic circuit 41 outputs the request source “1”
, An N-bit unsigned addition of + n to the output value (N bits) of the DFF 11 is executed. The arithmetic circuit 42 corresponds to the request source “2”, and outputs the output value (N bits) of the DFF 11
+ (N-1) is performed.
That is, when n = 2 ^N −1 and L is an integer from 0 to n, the L-th arithmetic circuit counting from 0 corresponds to the request source “L” and (output value of DFF 11) + ( n-L +
The N-bit unsigned addition of 1) is performed. Hereinafter, similarly, the arithmetic circuit 4n corresponds to the request source “n”, and the DFF
An N-bit unsigned addition of +1 to the output value (N bits) of 11 is executed. The output values of these arithmetic circuits 40 to 4n are input to the comparator 31. The comparator 31 compares all of these input values, and determines the maximum value among them in the arithmetic circuit 2.
Output to 1.

The calculation flow for the case where N = 3 and n = 7 will be described. When the output value of the DFF 11 at a certain time is “5”, the arithmetic circuits 40, 41, 4
The calculation output results of 2, 43, 44, 45, 46, and 47 are “5”, “4”, “3”, “2”,
"1", "0", "7", "6". Here, the position of “5” which is the previous round robin result, that is, the operation result of the operation circuit of reference numeral 45 (corresponding to the request source “5”) is 0.
And the priority in the next round robin process becomes the lowest, and the operation result of the operation circuit of the code 46 (corresponding to the request source “6”) following the code 45 is the maximum value of the 3-bit integer “7” Indicates that the priority is the highest. Therefore, if all requesters have issued requests, the largest value among them is naturally "7", and "7" is output from the comparator 31 as a comparison result. Then, in the arithmetic circuit 21, 5 [+8] −7 = 6 (in unsigned subtraction, a borrow is automatically generated when the solution becomes negative, and a carry is automatically discarded) Is calculated, and the latest round robin result as its output is “6”. This round robin result “6” is latched by the DFF 11 at the next rising edge of the clock signal,
It will be output as a round robin result. It can be seen that the round robin result is correct even when compared with the operation results of the operation circuits 40 to 47.

As described above, the arithmetic circuit 21, the comparator 31, and the arithmetic circuits 40 to 4n for realizing round robin are all composed of combinational circuits, and only the DFF 11 is a latch circuit responding to a clock signal. The robin process is completed in one clock.

Next, FIG. 3 shows a comparison value (N bits) for round robin shown in FIG. 1, a comparison value (M bits) presented by each requester concerning the arbitration algorithm, and a request value of each requester. An arbitration control circuit for collectively comparing a flag signal (valid display bit) indicating presence / absence and outputting a selection result is shown.

In FIG. 3, in addition to the comparison values for round robin from the plurality of arithmetic circuits 40 to 4n, the request sources "0" to "n" for the arbitration algorithm are sent to the comparator 31. Comparison numerical values to be presented (M bits each)
And valid display bits (one bit each) indicating whether or not there is a request from each request source. The valid display bit is "1" when the requester has issued a request, and is "0" when the requester has not issued the request. That is, the comparator 31 receives comparison numerical data combined into 1 + M + N bits corresponding to one request source.

As shown in FIG. 2, a valid display bit (valid / invalid bit) is arranged at the most significant bit, and M-bit comparison numerical data of the arbitration algorithm is arranged at the next higher bit, as shown in FIG. N bits of round robin (RR) are arranged in lower bits.

The comparator 31 compares n + 1 (2 ^N ) pieces of comparison numerical data (including valid display bits) having a (1 + M + N) bit width inputted corresponding to each request source as unsigned integer values. Search for the maximum value, and output the searched maximum value.

The comparison process in the comparator 31 will be described with reference to FIG. The comparison part of the comparison value of the arbitration algorithm may have any number of stages as long as the bit width of the comparator 31 permits. Even if the comparison value of the arbitration algorithm does not uniquely determine an option, the lower bits for round robin may be used. The choice is always uniquely determined by comparing the comparison values. In the comparison of numerical values, the higher-order bit largely influences the result, and if the upper-order bit is not determined, the lower-order bit is referred to. Therefore, by assigning the most significant bits to the higher-order bits, it is possible to collectively compare a plurality of factors and derive the result.

In FIG. 2, the valid / invalid bit is taken as the most significant bit, so that it can be determined first whether the requester has really issued the request. In the case of FIG. 2, since the comparator for searching for the maximum value is used, if this bit is 1 and the valid one is smaller than the invalid one, No side can be in any state. Similarly, among the bits whose effective bits are 1, the numerical values presented by the arbitration algorithm, which are the next lower few bits, are compared. The selection result is uniquely obtained by comparing the numerical values of the round robin. After all, even if the numerical comparison is performed collectively, it is the same value as performing such processing.

A more specific example will be described. FIG. 2 shows that N =
3, n = 7, that is, an example of the state of the comparison numerical value when there are eight (n + 1) request sources. First, 44 (corresponding to request source "4") and 46 (corresponding to request source "6") are dropped depending on whether the valid / invalid bit of the most significant bit is 1 or 0, and then presented to the arbitration algorithm. Comparing the obtained numerical values, 41 (corresponding to the request source “1”) and 47 (corresponding to the request source “7”) are 11, indicating the maximum value. At this stage, since it has not yet been uniquely determined, referring to a few bits of the last round robin, 41 (corresponding to the request source “1”) is 0, and 47 (corresponding to the request source “7”) is 2 Finally, 47 (corresponding to the request source "7") is selected.

On the right side of FIG. 2, these numerical values are actually shown in binary notation. Here, since the maximum value of the comparison value of the arbitration algorithm is 11, it is represented as M = 4. Since a collective numerical comparison is equivalent to searching for the largest one bit at a time starting from the most significant bit, looking at this from the top, the most significant bits are: 40, 41, 42, 43, 45 , 47 2nd bit: 41, 42, 47 3rd bit: 41, 42, 47 4th bit: 41, 47 5th bit: 41, 476 6th bit: 41, 477th bit: 478th bit: −, Which is naturally the same as the previous result.

Next, in FIG. 3, the lower N bits b of the output result (maximum value) of the comparator 31 are used by the next-stage arithmetic circuit 21 to calculate the final selection result.
The most significant bit of the output result (maximum value) of the comparator 31 is commonly input to an enable signal terminal of an N-bit latch circuit (DFF) 11 with an enable signal.

As described with reference to FIG. 1, the arithmetic circuit 21 performs an operation of subtracting the lower N bits b of the output result (maximum value) of the comparator 31 from the output a of the DFF 11 by an unsigned integer. The subtraction result (ab) is output to the DFF 11 as the latest arbitration result.

Also, the enable terminal of the DFF 11
Since the most significant bit of the output result (maximum value) of the comparator 31 is input, the arbitration result is latched only when the output result is valid. Therefore, when no request is issued from all request sources, the arbitration operation is not performed, and the arbitration result becomes an invalid value.

As described above, in the first embodiment,
In the arbitration algorithm that searches for and selects the maximum value and the arbitration including the round robin that finally narrows down the selection result uniquely when the result becomes more than one, the upper bits in the comparison numerical bits are used as the arbitration algorithm. An arbitration procedure based on an arbitration algorithm based on numerical comparison by making a value presented by each requester in relation to the lower order bit as a numerical value determined by round robin control, and comparing these collectively and searching for a maximum value. And round-robin narrowing down procedures can be performed simultaneously without stepping up a plurality of steps such as a plurality of clock steps, thereby simplifying the circuit and increasing the speed of the circuit. . Also, a flag signal indicating the presence / absence of a request from each requester is input to the comparator 31 as the most significant bit, and the most significant bit output of the comparator 31 is output to the latch circuit 11.
The arbitration operation is not executed when no request is issued from all request sources, so that an erroneous arbitration result is not output.

Embodiment 2 Next, a second embodiment of the present invention will be described with reference to FIG. In the second embodiment, the arbitration algorithm implements a round-robin function in a case where the arbitration algorithm selects the one outputting the minimum value among the numerical values presented by the request source. FIG. 4 shows a comparison value (N bits) for round robin, a comparison value (M bits) presented by each requester regarding the arbitration algorithm, a flag signal (valid display bit) indicating the presence or absence of a request from each requester. Are collectively compared to output an arbitration control circuit.

In FIG. 4, an N-bit latch circuit (D
FF) 11 is for latching a round robin result (N bits) indicating the selected request source with the clock signal as a trigger. In this case, the latch circuit 11
Has an enable signal terminal that is enabled when the input enable signal is 1 and disabled when the input enable signal is 0, as described above. The arithmetic circuit 22 adds the previous round robin result a (N bits) held by the DFF 11, the output N of the lower N bits of the comparator 32, and the value 1 as an unsigned integer, and adds the result (a + b + 1). ) Is output to the DFF 11 as the latest arbitration result.

The arithmetic circuits 50 to 5n (n = 2 ^N -1) respectively perform the operations shown in the frame on the input output value of the DFF 11, that is, the previous round robin result a (N bits), to perform round robin. Output the comparison numerical value for For example, the arithmetic circuit 50 corresponds to the request source “0”,
N that subtracts the output value a (N bits) of the DFF 11 from n
Perform bit unsigned subtraction (na). Arithmetic circuit 5
1 corresponds to the request source “1” and the output value a of the DFF 11
Perform N-bit unsigned subtraction (0-a) of subtracting (N bits) from 0. The arithmetic circuit 52 outputs the request source “2”
, The N-bit unsigned subtraction (1-a) of subtracting the output value a (N bits) of the DFF 11 from 1 is executed.
That is, when n = 2 ^N −1 and L is an integer from 0 to n, the L-th arithmetic circuit counting from 0 corresponds to the request source “L” and has N bits of (L + n−a). Performing unsigned addition. Hereinafter, similarly, the arithmetic circuit 5n corresponds to the request source "n" and outputs the output value (N bits) of the DFF 11.
Perform N-bit unsigned subtraction of subtracting a from (n-1). The output values of these arithmetic circuits 50 to 5n are
2 is input.

For the comparator 32, as in the first embodiment, in addition to the comparison values for round robin from the plurality of arithmetic circuits 50 to 5n, the request sources "0" to "0" for the arbitration algorithm are used. n ”(M bits each)
And valid display bits (one bit each) indicating whether or not there is a request from each request source. However, in this case,
Since the minimum value is selected, the valid display bit is the reverse of that of the first embodiment, and is “0” when the requester has issued the request, and “1” when the requester has not issued the request. ". As described above, the comparator 32 receives the comparison numerical data combined into 1 + M + N bits corresponding to one request source.

As shown in FIG. 2, the valid bit (valid / invalid bit) is placed at the most significant bit, and the M-bit comparison numerical data of the arbitration algorithm is placed at the next higher bit. Then, N bits of round robin (RR) are arranged in the lower bits.

The comparator 32 compares n + 1 (2 ^N ) pieces of comparison numerical data (including valid display bits) having a (1 + M + N) bit width and corresponding to each request source as unsigned integer values. Search for the minimum value, and output the searched minimum value.

The lower N bits b of the output result (maximum value) of the comparator 32 are used by the next-stage arithmetic circuit 22 to calculate the final selection result. That is, the operation circuit 22
Then, the output a (N bits) of the DFF 11 and the comparator 32
Of the lower N bits and the value 1 as an unsigned integer, and outputs the addition result (a + b + 1) to the DFF 11 as the latest arbitration result.

The most significant bit of the output result (maximum value) of the comparator 32 is input to the inverter 23, and the value logically inverted by the inverter 23 is used as an enable signal for an N-bit latch circuit (DFF) 11 Are commonly input to the enable signal terminal of Thus, also in this case, D
Since the most significant bit of the output result (minimum value) of the comparator 32 is input to the enable terminal of the FF 11, the arbitration result is latched only when the output result is valid. Therefore, when no request is issued from all request sources, the arbitration operation is not performed, and the arbitration result becomes an invalid value.

Next, the flow of calculation in which the comparator 32 calculates the minimum value will be described. N = 3, n = 7, DF
Assuming that the value currently latched in F11 is “4”, the arithmetic outputs of the arithmetic circuits 50 to 57 are “3”, “4”, “5”, “6”, “7”, “7”, respectively. 0 ",
"1" and "2". Here, the position of “4”, which is the previous round robin result, that is, the calculation result of the calculation circuit of the code 54 (corresponding to the request source “4”) is the maximum value 7 of a 3-bit integer, and the minimum value is Because it is a circuit to search, the priority in the next round robin processing is the lowest,
The operation result of the operation circuit of the code 55 (corresponding to the request source “5”) following the code 54 indicates the minimum “0”, and the priority is the highest. Therefore, if all requesters have issued requests, the smallest value among them is naturally "0", and "0" is output from the comparator 32 as a comparison result. Then, in the arithmetic circuit 22, 4 + 0 + 1 = 5
(3-bit unsigned addition) is calculated, and the latest round robin result as its output is “5”. This round robin result “5” is latched by the DFF 11 at the next rising edge of the clock signal, and is output as the round robin result. It can be seen that the round robin result is correct even when compared with the operation results of the operation circuits 50 to 57.

As described above, in the second embodiment,
In the arbitration algorithm that searches for and selects the minimum value and the arbitration that includes a round robin to finally narrow down the selection result when the number of results is more than one, the upper bits of the comparison numerical bits are used as the arbitration algorithm. An arbitration procedure based on an arbitration algorithm based on a numerical comparison, in which a value presented by each requester in relation to the lower order bit is a numerical value determined by round robin control, and these are collectively compared to search for a minimum value. And round-robin narrowing down procedures can be performed simultaneously without stepping up a plurality of steps such as a plurality of clock steps, thereby simplifying the circuit and increasing the speed of the circuit. . Further, a flag signal indicating the presence / absence of a request from each requester is input to the comparator 32 as the most significant bit, and the most significant bit output of the comparator 32 is logically inverted and input to the latch circuit (DFF) 11 as an enable signal. By doing so, if no request is issued from all request sources, the arbitration operation is prevented from being executed, so that an erroneous arbitration result is not output.

Embodiment 3 FIG. Next, a third embodiment of the present invention will be described. Normally, a comparator outputs a first type that outputs a comparison result of a plurality of input values and a second type that outputs number data corresponding to an input value selected as a result of the comparison or a decoded version of the number. There are two types:

For example, in a comparator in which a comparison is made at any time in a tournament format to search for a maximum or a minimum, 1
Since it is necessary to perform the comparison again after the second comparison, the first type in which the value output as the result of the comparison is the comparison value itself and the comparison result of the final stage is also output as it is.

On the other hand, when all values are compared and the comparison result is output all at once, there is no need to transmit the comparison value to the next, so that the flag corresponding to the number data of the input value is valid or invalid. You will get a comparison result. That is,
In this case, for example, there are 0 to 7 comparison targets, and eight signals are prepared for outputting the comparison result, and only one signal line corresponding to the comparison target number indicating the maximum or the minimum is set to 1 It will be shaky. In this case, by encoding the result into a numerical value, a comparator that outputs number data (0 to n) corresponding to the maximum or minimum comparison value can be realized.

If such a second type of comparator is used, the output of the comparator will be the final arbitration result. Therefore, when employing the maximum value selection method, the arithmetic circuit 21 of FIG. 1 can be omitted. When the minimum value selection method is adopted, the arithmetic circuit 22 shown in FIG. 4 can be omitted. Then, the output of the comparator may be directly input to the DFF 11.

In the third embodiment, as in the previous embodiment, the arbitration procedure based on the arbitration algorithm based on numerical comparison and the narrowing-down procedure based on round robin are simultaneously executed without performing a plurality of steps such as a plurality of clock steps. It is possible to do.

[0063]

As described above, according to the arbitration control method according to the present invention, an arbitration algorithm for retrieving and selecting a maximum value or a minimum value and finally selecting a result when a plurality of results are obtained. In the arbitration including the round robin for uniquely narrowing down, the upper bits in the comparison numerical bits are set to the values presented by each requester in relation to the arbitration algorithm, and the lower bits are set to the numbers determined by the round robin control, By comparing these at once, the arbitration procedure using the arbitration algorithm based on numerical comparison and the narrowing-down procedure based on round robin can be performed simultaneously without performing multiple steps such as multiple clock steps. Simple simplification of the
It is possible to realize a high-speed circuit and the like.

According to the next invention, in the arbitration control circuit for determining one request source outputting the maximum value, a latch circuit for latching an N-bit arbitration result by a clock signal, and an output from the latch circuit A plurality of first arithmetic circuits for performing different unsigned integer arithmetic operations on the previous arbitration result and outputting comparison numerical data for round robin;
M + N bits of combined data for a plurality of request sources obtained by combining N-bit output from each first arithmetic circuit as lower bits and M-bit comparison numerical data presented by each requester as an upper bit for an arbitration algorithm And a comparator that outputs the maximum value by comparing as an unsigned integer, and subtracts, without sign, the value indicated by the lower N bits of the output of the comparator from the previous arbitration result output from the latch circuit. A second arithmetic circuit for inputting the subtraction result to the latch circuit as a current arbitration result, and collectively executing an arbitration algorithm for searching for a maximum value and round robin in one clock cycle to obtain only one arbitration result. Since the arbitration control circuit is derived, an arbitration control circuit having a simple configuration and capable of high-speed processing can be realized.

According to the arbitration control circuit of the next invention, the first arithmetic circuit outputs (n−L +
By adding 1), round-robin comparison numerical data corresponding to the L-th request source is output, so high-speed processing is possible with a simple configuration and high-precision arbitration can be achieved. An arbitration control circuit can be embodied.

According to the arbitration control circuit of the next invention, a flag signal indicating the presence / absence of a request from each requester is input to the comparator as the most significant bit, and the most significant bit output of the comparator is sent to the latch circuit. By inputting as an enable signal, when no request is issued from all request sources, the arbitration operation is prevented from being executed, so that an erroneous arbitration result is not output.

According to the arbitration control circuit according to the next invention, the comparator outputs the request source number data corresponding to the maximum value as the arbitration result. It is possible to omit an arithmetic circuit for calculating the request source to be performed, thereby making it possible to further simplify the circuit, increase the speed of the circuit, and the like.

According to the arbitration control circuit of the next invention, in the arbitration control circuit for determining one request source outputting the minimum value, a latch circuit for latching an N-bit arbitration result by a clock signal; A plurality of first arithmetic circuits that perform different unsigned integer arithmetic operations on the previous arbitration results output from the circuits and output round-robin comparison numerical data, and an N-bit output from each first arithmetic circuit. Combined data of a plurality of request sources, each of which is composed of lower-order bits and M-bit comparison numerical data presented by each requester for the arbitration algorithm as upper-order bits, is represented by M
A comparator that outputs a minimum value by comparing as a + N-bit unsigned integer, and outputs a value indicated by the lower N bits of the output of the comparator and a previous arbitration result output from the latch circuit without a sign. A second arithmetic circuit that outputs the current arbitration result based on the addition.
Since the arbitration algorithm for searching for the minimum value and round robin are collectively executed to derive only one arbitration result, an arbitration control circuit that can perform high-speed processing with a simple configuration can be realized. .

According to the arbitration control circuit of the next invention, the first arithmetic circuit subtracts the output of the latch circuit from the value (L + n) to obtain the round-robin for the L-th request source. Output comparative numerical data,
Calculates the current arbitration result based on the unsigned addition of the value indicated by the lower N bits of the output of the comparator, the previous arbitration result output from the latch circuit, and the value 1. As a result, an arbitration control circuit capable of performing high-speed processing and performing highly accurate arbitration with a simple configuration can be realized.

According to the arbitration control circuit of the next invention, a flag signal indicating whether or not each requester has a request is input to the comparator as the most significant bit, and the most significant bit output of the comparator is logically inverted. By inputting it as an enable signal to the latch circuit, if no request has been issued from all request sources, the arbitration operation is prevented from being executed.
Incorrect arbitration results will not be output.

According to the arbitration control circuit according to the next invention, the comparator outputs the request source number data corresponding to the minimum value as the arbitration result. It is possible to omit an arithmetic circuit for calculating the request source to be performed, thereby making it possible to further simplify the circuit, increase the speed of the circuit, and the like.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a first embodiment of an arbitration control circuit according to the present invention, and is a block diagram particularly illustrating only a portion related to round robin;

FIG. 2 is a diagram showing comparative numerical data in which a comparative numerical value by an arbitration algorithm is used for upper bits and a comparative numerical value by round robin is used for lower bits.

FIG. 3 is a block diagram illustrating a first embodiment of an arbitration control circuit according to the present invention;

FIG. 4 is a block diagram showing a second embodiment of the arbitration control circuit according to the present invention;

[Explanation of symbols]

Reference Signs List 11 latch circuit (D-type flip-flop), 21 operation circuit (second operation circuit), 22 operation circuit (second operation circuit), 31 comparator, 32 comparator, 40 to 4n
Arithmetic circuit (first arithmetic circuit), 50 to 5n arithmetic circuit (first arithmetic circuit).

Claims (9)

[Claims] 1. A arbitration algorithm that selects a maximum value or a minimum value from data values presented by a plurality of request sources and selects a request source presenting the maximum value or the minimum value as a selection result, In the arbitration control method using round-robin control to finally determine one request source when a value or a value corresponding to the minimum value is presented from a plurality of request sources, the upper M bits are used for an arbitration algorithm. Is the first comparison numerical data presented by each requester, and the lower N bits are round robins composed of all different N-bit integer values obtained by subjecting the previous arbitration result to different predetermined calculations for each requester. By comparing the first and second comparison numerical data for a plurality of request sources as M + N-bit unsigned integers, as second comparison numerical data for Arbitration control method characterized by finding the current arbitration results based on that search for maximum value or the minimum value of over data. 2. A method for selecting a maximum value among data values presented by a plurality of request sources and applying the arbitration algorithm to select a request source presenting the maximum value as a selection result, wherein a value corresponding to the maximum value is An arbitration control circuit that uses round-robin control to finally determine one request source when presented from a plurality of request sources; a latch circuit that latches an N-bit arbitration result using a clock signal as a trigger; A plurality of first arithmetic circuits that perform different unsigned integer arithmetic operations on the previous arbitration result output from the latch circuit and output round-robin comparison numerical data including integer values of N bits different from each other; The N-bit output from each of the first arithmetic circuits is set as a lower bit, and the M-bit comparison numerical data presented by each requester for the arbitration algorithm is set as an upper bit. A comparator for comparing the combined data of the plurality of request sources as M + N-bit unsigned integers and outputting a maximum value; and a value indicated by the lower N bits of the output of the comparator, And a second arithmetic circuit for inputting the subtraction result as a current arbitration result to the latch circuit, and searching for the maximum value in one clock cycle. An arbitration control circuit for executing an algorithm and round robin collectively to derive a unique arbitration result. 3. When n = 2 ^N -1 and L is an integer from 0 to n, each of the first arithmetic circuits adds (n−L + 1) to the output of the latch circuit. , L
The arbitration control circuit according to claim 2, wherein the arbitration control circuit outputs round-robin comparison numerical data corresponding to the request source. 4. A comparator according to claim 1, wherein a flag signal indicating the presence / absence of a request from each requester is input as the most significant bit, and an output of the most significant bit of the comparator is input to the latch circuit as an enable signal. The arbitration control circuit according to claim 2 or 3, wherein 5. A arbitration algorithm which selects a maximum value among data values presented by a plurality of request sources and selects the request source presenting the maximum value as a selection result, wherein a value corresponding to the maximum value is obtained. An arbitration control circuit that uses round-robin control to finally determine one request source when presented from a plurality of request sources; a latch circuit that latches an N-bit arbitration result using a clock signal as a trigger; A plurality of arithmetic circuits for performing different unsigned integer arithmetic operations on the previous arbitration results output from the latch circuit and outputting round-robin comparison numerical data including integer values of N bits different from each other; The N-bit output from the circuit is used as the lower bits, and the M-bit comparison numerical data presented by each requester for the arbitration algorithm is synthesized as the upper bits. The combined data for the plurality of request sources are compared as unsigned integers of M + N bits, the number of the request source having the maximum value is output by this comparison, and the number data is input to the latch circuit as a result of the current arbitration. An arbitration control circuit comprising: a comparator; and an arbitration algorithm for searching for a maximum value and round robin are collectively executed in one clock cycle to derive a unique arbitration result. 6. A arbitration algorithm which selects a minimum value among data values presented by a plurality of request sources and selects a request source presenting the minimum value as a selection result, wherein a value corresponding to the minimum value is obtained. An arbitration control circuit that uses round-robin control to finally determine one request source when presented from a plurality of request sources; a latch circuit that latches an N-bit arbitration result using a clock signal as a trigger; A plurality of first arithmetic circuits that perform different unsigned integer arithmetic operations on the previous arbitration result output from the latch circuit and output round-robin comparison numerical data including integer values of N bits different from each other; The N-bit output from each of the first arithmetic circuits is set as a lower bit, and the M-bit comparison numerical data presented by each requester for the arbitration algorithm is set as an upper bit. A comparator for comparing the combined data of the plurality of request sources combined as unsigned integers of M + N bits and outputting a minimum value; a value indicated by the lower N bits of the output of the comparator; A second arithmetic circuit that obtains the current arbitration result based on the unsigned addition of the previous arbitration result output from the arbitration result and inputs the current arbitration result to the latch circuit. And an arbitration control circuit characterized in that an arbitration algorithm for searching for a minimum value and round robin are collectively executed to derive a unique arbitration result. 7. When n = 2 ^N -1 and L is an integer from 0 to n, each of the first arithmetic circuits has a value (L +
n) by subtracting the output of the latch circuit from
Outputting comparison numerical data for round robin corresponding to the L-th request source, wherein the second arithmetic circuit outputs the value indicated by the lower N bits of the output of the comparator and the latch circuit 7. The arbitration control circuit according to claim 6, wherein the current arbitration result is obtained based on an unsigned addition of the previous arbitration result and the value 1. 8. A flag signal indicating the presence / absence of a request from each requester is input to the comparator as the most significant bit, and the most significant bit output of the comparator is logically inverted and input to the latch circuit as an enable signal. 7. The method according to claim 6, wherein
Or the arbitration control circuit according to 7. 9. A arbitration algorithm which selects a minimum value among data values presented by a plurality of request sources and selects a request source presenting the minimum value as a selection result, wherein a value corresponding to the minimum value is obtained. An arbitration control circuit that uses round-robin control to finally determine one request source when presented from a plurality of request sources; a latch circuit that latches an N-bit arbitration result using a clock signal as a trigger; A plurality of arithmetic circuits for performing different unsigned integer arithmetic operations on the previous arbitration results output from the latch circuit and outputting round-robin comparison numerical data including integer values of N bits different from each other; The N-bit output from the circuit is used as the lower bits, and the M-bit comparison numerical data presented by each requester for the arbitration algorithm is synthesized as the upper bits. The combined data of the plurality of request sources are compared as unsigned integers of M + N bits, and the number of the request source which becomes the minimum value by this comparison is output. An arbitration control circuit comprising: a comparator; and an arbitration algorithm for searching for a minimum value and round robin are collectively executed in one clock cycle to derive a unique arbitration result.