TWI423121B - System and method for determination of a horizontal minimum of digital values - Google Patents

Description

Judging system and method

The present invention relates to a microprocessor instruction, and more particularly to a system and method for determining a minimum code from a set of digital values, wherein the smallest digit code is used as a horizontal minimum. (horizontal minimum).

Current microprocessors are often used to execute Media Instructions to increase the efficiency of multimedia applications. For example, the microprocessor architecture may include one or more media instructions to identify a level minimum from a set of digit codes, and the level minimum is in a bus or a register. The corresponding location of (register). A specific example is the PHMINPOSUW instruction in Intel's SSE4 programming reference manual. The PHMINPOSUW instruction finds the corresponding position of the smallest character and the smallest character from 8 unsigned words (128 bits), wherein the smallest character has 16 bits. Some conventional microprocessors require more processing or more clock cycles when executing the PHMINPOSUW instruction. For example, in order to identify the smallest pair of characters in a plurality of pairs of characters, it is necessary to use four 16-bit magnitude comparators in order to have a search range of eight in a first cycle. The character is reduced to 4 characters, and the found 4 characters are fed back to 2 comparators, and the search range is reduced from 4 characters to 2 in a second period. The character is finally returned to the comparator for finding the smallest character of the two characters in a third (ie, last) period. In a conventional practice, the function of executing instructions in a single cycle is achieved by increasing the number of 16-bit comparators. Taking seven 16-bit comparators as an example, in a single cycle, the first comparison is performed using four comparators to reduce the search range from 8 characters to 4 characters, and then use 2 The comparator reduces the search range from 4 characters to 2 characters, and finally uses the 1 comparator to find the smallest one from the 2 characters. However, each 16-bit comparator consumes a large amount of space in the microprocessor, thereby increasing cost and processing efficiency.

It is an object of the present invention to find the smallest digit code and its corresponding position from a set of digital codes in a single cycle without adding circuitry.

The present invention provides a judging system for finding a minimum binary code from at least two binary codes. In one embodiment, the determination system includes a first adder, a second adder, and a comparison circuit. The first adder adds a plurality of first bits and a plurality of second bits to provide a first carry output and a first transfer output. The first bit is a high bit of a first binary code. The second bits are inverted to the upper bits of a second binary code. The second adder adds a total of the third bit and the complex fourth bit to provide a second carry output. The third bit is the lower bit of the first binary code. The fourth bit is inverted to the lower bit of the second binary code. The comparison circuit determines whether the first binary code is greater than the second binary code based on the first and second carry outputs and the first transfer output. Both the first and second binary codes have no sign (unsigned). The first and second adders perform an unsigned binary addition. The first delivery output represents whether the first adder receives a carry input.

The present invention further provides a determination system for quickly finding a horizontal minimum from a plurality of digital code. The judgment system of the present invention includes a complex difference circuit, a path selection circuit, and a comparison circuit. Each difference circuit compares two digit codes. A path selection circuit assigns each of the digital code to at least one difference circuit for comparing each digital code with another digital code. Each difference circuit may include a high adder and a low adder. The high adder compares the high portion of the first digit code with the high portion of the second digit code to provide a first carry output and a pass output. The low adder compares the low portion of the first digit code with the low portion of the second digit code to provide a second carry output. The comparison circuit compares the first and second carry outputs and compares the transfer outputs for learning one of the lowest digit codes of the digital code.

Each pass output indicates whether the high adder of one of the difference circuits receives a carry input. The comparison circuit includes a decoding circuit. The decoding circuit decodes the compare bits to provide a complex minimum bit. Each minimum bit indicates whether the corresponding digit code is the least digit code. A position circuit informs the memory location of the least digit code. The decision system may be integrated into a microprocessor die to perform a fast horizontal minimum command.

The present invention provides a method of determining to find one of the plurality of digit codes. In a possible embodiment, the determining method includes the steps of comparing a high bit of a first digit code and a high bit of a second digit code to provide a first carry output and a pass output; comparing the first digit a lower bit of the code and a lower bit of the second digit code for providing a second carry output; and determining, according to the first and second carry outputs and the transfer output, that the first or second digit code system is Smaller code. The method of determining the present invention may include transmitting each of the digit codes to at least one adder pair of the complex adder pair to compare each digit code with another digit code to learn a minimum Digital code. The judging method of the present invention further includes decoding the comparison bit. The judging method of the present invention further includes knowing the position of the least digit code in a memory.

The present invention provides a system for performing a horizontal minimum command and an error absolute value summation command using a common adder circuit. In one embodiment, the system includes a complex adder, a summing circuit, a comparison circuit, and a path selection circuit. The input operand includes a complex digit code. For an error absolute value sum instruction, the digital code includes a first digital code set and a second digital code set. For horizontal minimum instructions, the digital code includes a complex digital code pair. Each digit code pair has a high digit code and a low digit code. Each adder compares a first digit code with a second digit code to provide an absolute value of the error and a carry output. The summing circuit sums the absolute values of the errors to provide an absolute value of the complex errors plus the total value. The adders form a complex adder pair and provide a transfer output. The comparison circuit combines the carry outputs and the pass outputs to find a minimum digit code pair of the pair of digits. When the horizontal minimum instruction is executed, the path selection circuit transmits each digital code pair of the digital code pair to at least one adder pair of the adder pair for pairing each digital code pair with another digital code pair Compared. When the error absolute value sum command is executed, the path selection circuit transmits the first and second digit code sets to the adder pair to learn each digit code of the first digit code set and the second An absolute value of the error between each digit code of the set of digits, the second set of digits having a continuous digit code.

The present invention further provides a method for performing a horizontal minimum command and an error absolute value summation command using a common adder circuit. In an embodiment, the method provided by the present invention includes receiving a complex digital code. When the error absolute value summation instruction is executed, the digit code includes a first digit code set and a second digit code set. When the horizontal minimum command is executed, the digital code includes a high digit code and a low digit code. The method provided by the present invention further includes providing a complex adder. Each adder compares a first digit code with a second digit code to provide an absolute value of the error and a carry output. The method provided by the present invention further comprises: summing the absolute values of the errors to provide a sum of absolute values of the complex errors; classifying the adders into a complex adder pair and providing a transfer output; combining the carry outputs And the pass output for learning a minimum number of bit pairs of the pair of digits; and, when the minimum instruction is executed, transmitting each pair of pairs of the pair of digits to the pair of adders At least one adder pair for comparing each digit code pair with another digit code pair, and transmitting the first and second digit code sets to the adder pair when performing the error absolute value sum instruction And an absolute value of the error between each digit code of the first digit code set and each consecutive digit code of the second digit code set.

The following examples are presented to enable one of ordinary skill in the art to make and use the present disclosure. Modifications of the preferred embodiments will be apparent to those skilled in the art, and the general principles described herein are applicable to other embodiments. Therefore, the invention is not limited to the specific embodiments set forth and described herein, which are to

The present invention notes that conventional microprocessors require a number of cycles to execute a horizontal minimum instruction. The present invention requires only a single cycle when executing the same instructions, and does not add a large amount of circuitry. The present invention provides a system and method for quickly knowing the minimum level of the present invention. In order to make the features and advantages of the present invention more apparent, the preferred embodiments are described below, and the drawings are incorporated. 8 figure), for a detailed description.

FIG. 1 is a block diagram of a microprocessor 100 in accordance with an embodiment of the present invention. The processor 100 has a comparison circuit 114. The comparison circuit 114 can quickly find a horizontal minimum value from the digital code set, and obtain sum of absolute differences of the first digital code set and the second digital code set. . In this embodiment, FIG. 1 does not show other conventional systems and functions, such as instruction fetch, instruction queue, instruction decoding, and instruction reordering. )…Wait. Although FIG. 1 does not show some of the prior art, it does not affect the understanding of the present invention. The microprocessor 100 has a scheduler 102. The scheduler 102 routes or commands a program for selecting arithmetic logic units (ALUs) or execution units (EUs). As shown in FIG. 1, the scheduler 102 is coupled to a complex integer execution unit (IEU) 104, a simple integer execution unit (simple IEU) 106, and a floating point execution unit (FPEU) 108. The media unit 110 and other units 112, wherein the other units 112 are other similar or different processing units. Media unit 110 typically performs media-based instructions and operations, such as Streaming SIMD Extensions (SSE) or MultiMedia extension (MMX) and other similar instruction sets. SSE is a SIMD instruction set in Intel's x86 architecture, and SIMD refers to single instruction multiple data. The media unit 110 has a comparison circuit 114 for executing at least two independent media instructions. In the present embodiment, the two media instructions are referred to as a horizontal minimum instruction (PMIN instruction) and an error absolute value sum instruction (PSAD instruction). The PSAD instruction represents a sum of absolute values of errors of a first set of digital code (or binary code) and a second set of digital code (or binary code), wherein the second set of digital codes follows the first set of digital codes. The first digit code set and the second digit code set will be described in detail later. By executing the PMIN command, a minimum digit code and its corresponding position can be known. In this embodiment, the above-mentioned digital code, binary code and corresponding format are mutually replaceable, and these codes represent complex bits or hexadecimal digit codes. The scheduler 102 has a memory 116. The memory 116 is used to store operands of the PSAD instruction and the PMIN instruction, and has a first bus ABUS and a second bus BBUS. In an embodiment, the first bus ABUS and the second bus BBUS can transmit 128 bits, but are not intended to limit the present invention. In other embodiments, the first bus ABUS and the second bus BBUS can transmit other numbers of bits. Although the media unit 110 is typically used to perform a variety of other media instructions known to those skilled in the art, the comparison circuit 114 is operative to execute the PSAD and PMIN instructions.

In a possible embodiment, for the PSAD instruction, the first digit code set has 4 bytes (each byte has 8 bits), wherein the 4 bytes are unsigned bits. Tuple. For the PSAD instruction, the second set of digit codes has a set of one tuples. This byte set has 11 consecutive bytes. At the same time, every 4 consecutive bytes are classified into a group. For the second digit code set, each next 4-byte group starts with the next higher byte, meaning that each next group is shifted by 1 byte, so it will overlap. The last 3 bytes of a group. Assume that the second digit code set has 11 bytes B0~B10. First, B0~B3 are classified into the first group, and then, the next higher byte (such as B1) is started, and then classified into the second group (B1~B4). Therefore, the second group (B1~B4) overlaps the last three bytes (B1~B3) of the first group (B0~B3). The difference between each tuple of the first set of digits and each tuple of the second set of digits is referred to as the absolute value of the error. The absolute values of the above errors will be added together. A specific example is the MPSADBW instruction in Intel's SSE4 Program Reference Manual. For the PSAD instruction, the first bus ABUS transmits the first operand. The first operand includes 4 unsigned bins. The second bus BBUS transmits the second operand. The second operand has 11 unsigned bins. The sum of the absolute values of the errors is 8 unsigned 10-bit binary codes. The PSAD instruction may include one or more offsets to find the above operands. The present invention does not limit the magnitude of the offset. Any offset can be configured through the first bus ABUS and the second bus BBUS. Therefore, the corresponding operands are configured in the first bus ABUS and the first bus. The right-most bit position of the second bus BBUS. In the present embodiment, the above offset amount is omitted. In one embodiment, the PMIN instruction provides a minimum of eight unsigned digits in the first bus ABUS and a corresponding location of the minimum, wherein each of the eight unsigned digits The element has 16 bits. A specific example is the PHMINPOSUW instruction in Intel's SSE4 Program Reference Manual. For the PMIN instruction, the first bus ABUS transmits 8 characters, each of which has 16 bits. The bits transmitted by the second bus BBUS may not be defined or ignored, or the characters transmitted by the second bus BBUS may be the same as the first bus ABUS. In the present embodiment, the comparison circuit 114 executes the dual instructions (PMIN instruction and PSAD instruction) using the same adder circuit in a single cycle.

Figure 2 is an embodiment of the comparison circuit 114 of the present invention. As shown, the comparison circuit 114 includes a routing circuit 202, a low-order (LO) adder circuit 203, a high-order (HI) adder circuit 207, and a high-order/low-order Comparator circuit 212. The path selection circuit 202 has two input ends, which are respectively coupled to the first bus ABUS and the second bus BBUS. Path selection circuit 202 has another input for receiving control code INSTR. The path selection circuit 202 rearranges or re-selects the byte from the first bus ABUS and the second bus BBUS according to the control code INSTR received by the input terminal, and divides the first bus bar. The ABUS and the second bus BBUS byte. The control code INSTR has at least 1 bit. In the present embodiment, when the control code INSTR is equal to 1, it indicates that the PMIN instruction is executed; when the control code INSTR is equal to 0, it indicates that the PSAD instruction is executed. The first bus ABUS is divided into a high bit portion AH<31:0> and a low bit portion AL<31:0>, wherein the high bit portion AH<31:0> and the low bit portion AL<31:0> Both have 32 bits. The second bus bar BBUS is divided into a high bit portion BH<55:0> and a low bit portion BL<55:0>, wherein the high bit portion BH<55:0> and the low bit portion BL<55:0> Both have 56 bits. How to rearrange or re-select the bytes of the first bus ABUS and the second bus BBUS according to the instructions executed at the beginning will be described in detail later. The low order adder circuit 203 has a first adder circuit 204. The first adder circuit 204 is coupled to the first PMIN circuit 206. The high order adder circuit 207 has a second adder circuit 208. The second adder circuit 208 is coupled to the second PMIN circuit 210.

The first adder circuit 204 receives the control code INSTR, the lower bit portions AL<31:0> and BL<55:0>, and outputs the sum of the absolute values of the errors, PSAD<39:0>, and the comparison bits C<5:0>. . The sum of the absolute values of the errors, PSAD<39:0>, has 40 bits. The compare bit C<5:0> has 6 bits. The compare bits C<5:0>, AL<15:0>, and BL<47:0> are transferred to the first PMIN circuit 206. For the lower bit portion, the first PMIN circuit 206 outputs the minimum value PMINVAL<15:0> and the corresponding position PMINLOC<1:0>. The control code INSTR, the high bit portions AH<31:0> and BH<55:0> are transferred to the second adder circuit 208. The second adder circuit 208 outputs the sum of the absolute values of the errors, PSAD<79:40>, and the comparison bits C<11:6>. The sum of the absolute values of the errors PSAD<79:40> has 40 bits. The comparison bit C<11:6> has 6 bits. The compare bits C<11:6>, AH<15:0>, and BH<47:0> are transferred to the second PMIN circuit 210. For the high bit portion, the second PMIN circuit 210 outputs the minimum value PMINVAL<31:16> and the corresponding position PMINLOC<3:2>. The minimum value PMINVAL<15:0> and the corresponding position PMINLOC<1:0> output by the first PMIN circuit 206 and the minimum value PMINVAL<31:16> output by the second PMIN circuit 210 and the corresponding position PMINLOC< When 3:2> is combined, PMINVAL<31:0> and PMINLOC<3:0> can be generated. The high order/low order comparator circuit 212 receives PMINVAL<31:0> and PMINLOC<3:0> and produces the final minimum digit code MINVAL<15:0> and its relative position MINLOC<2:0>.

The first adder circuit 204 and the second adder circuit 208 arrange the input byte groups according to the instruction (ie, the control code INSTR) and perform a comparison between the bit groups. For the PSAD instruction, the combined PSAD<79:0> has eight 10-bit digit codes, where these digit codes have no sign. These eight 10-bit digit codes are the result of the sum of the absolute values of the execution errors. The first PMIN circuit 206, the second PMIN circuit 210, and the high order/low order comparator circuit 212 may be omitted for the PSAD instruction. For the PMIN instruction, when each high bit portion and low bit portion are input, PSAD<79:0> may be omitted, and the comparison bit C<11 received by the first PMIN circuit 206 and the second PMIN circuit 210 is: 0>, you can know the smallest digit code and relative position. When the first bus ABUS provides 128-bit input data, the high-order/low-order comparator circuit 212 receives and compares the lowest digits of the high-order portion and the low-order portion, and outputs the minimum value MINVAL<15:0> and relative Location MINLOC<2:0>.

Figure 3 is an embodiment of the path selection circuit 202 of the present invention. The path selection circuit 202 is configured to arrange or re-route the digital code provided by the first bus ABUS and the second bus BBUS according to a specific instruction. The buffer circuit 302 receives ABUS<31:0> and outputs a corresponding AL<31:0> for the PSAD instruction and the PMIN instruction. In an embodiment, for each bit, buffer circuit 302 can include a separate buffer such that ABUS<31:0> can be effectively copied to AL<31:0>. In other words, AL<31>=ABUS<31>, AL<30>=ABUS<30>,...,AL<0>=ABUS<0>. For the PSAD instruction and the PMIN instruction, AL<31:0> has 4 bytes A3~A0. For the PMIN instruction, the bytes A3~A0 can be divided into two pairs, wherein A3 and A2 can form the character W1, and A1 and A0 can form the character W0. The characters W1 and W0 each have 16 bits. The multiplexer 304 receives ABUS<95:64> and ABUS<31:0>. When the control signal of multiplexer 304 is equal to logic 1 (or high level), the output AH<31:0> of multiplexer 304 is equal to ABUS<95:64>. When the control signal of multiplexer 304 is equal to logic 0 (or low level), the output AH<31:0> of multiplexer 304 is equal to ABUS<31:0>. In one embodiment, a separate multiplexer having a 1-bit width is provided for each of the 32-bit AH<31:0> bits, thus having an input for each input and output. A separate multiplexer path (MUX path). If the control code INSTR represents the PMIN command, the multiplexer 304 takes ABUS<95:64> as AH<31:0>. These 32 bits form 4 bytes A11~A8. For PMIN, the bytes A11~A8 can be divided into two characters, wherein the bytes A11 and A10 can constitute the character W5, and the bytes A9 and A8 can constitute the character W4. If the control code INSTR represents PSAD, the multiplexer 304 takes ABUS<31:0> as AH<31:0>. These 32 bits form 4 bytes A3~A0. The copying of the byte is because the first operand of the PSAD instruction is the same for the high-order and low-order parts, as will be described in detail later.

When the control signal of the multiplexer 306 is logic 1 (ie, the control code INSTR=1), the multiplexer 306 receives and outputs 8 high bits 0x8 and ABUS<63:16>, wherein the logic of the 8 high bits 0x8 The value is 0. At this time, the output BL<55:0> of the multiplexer 306 is 8 high bits 0x8 and ABUS<63:16>. When the control signal of the multiplexer 306 is logic 0, the multiplexer 306 receives and outputs BBUS<55:0>. At this time, the output BL<55:0> of the multiplexer 306 is BBUS<55:0>. In an embodiment, a multiplexer having a 1-bit width may be used for each byte of each bus. If the control code INSTR represents the PMIN instruction, then ABUS<63:16> will be selected. ABUS<63:16> has 6 bytes A7~A2. The bytes A7~A2 can be respectively 3 pairs. Bytes A7 and A6 can form a character W3. Bytes A5 and A4 can form a character W2. The bytes A3 and A2 can form the character W1. If the control code INSTR represents the PSAD instruction, BBUS<55:0> will be selected. BBUS<55:0> has the second operand of the 7 lower bytes B6~B0. When the control terminal of the multiplexer 308 is logic 1, the multiplexer 308 receives and outputs 8 high bits 0x8 and ABUS<127:79>, wherein the logical values of the 8 high bits 0x8 are all 0. At this time, the output BH<55:0> of the multiplexer 308 is a combination of 8 high bits 0x8 and ABUS<127:79>. When the control terminal of the multiplexer 308 is logic 0, the multiplexer 308 receives and outputs BBUS<87:32>. At this time, the output BH<55:0> of the multiplexer 308 is BBUS<87:32>. If the control code INSTR is the PMIN instruction, ABUS<127:79> will be selected. ABUS<127:79> has 6 bytes A15~A10. The bytes A15~A10 can be 3 pairs respectively. The bytes A15 and A14 can form the character W7. The bytes A13 and A12 can constitute a character W6. The bytes A11 and A10 can constitute a character W5. If the control code INSTR is a PSAD instruction, BBUS<87:32> will be selected. BBUS<87:32> has 7 high-order bytes B10~B4, and 7 high-order bytes B10~B4 constitute the second operand of the PSAD instruction.

Referring to FIG. 2, for the PMIN instruction, using the selection of the path selection circuit 202 shown in FIG. 3, the characters W1 and W0 can be supplied to the AL bus, and the characters W3 to W1 can be supplied to the BL bus. For transmission to the first adder circuit 204. The first adder circuit 204 compares the character W0 with the characters W1 to W3, respectively, and compares the character W1 with the characters W2 to W3, and then compares the character W2 with the character W3, and according to Comparing the results, the corresponding comparison bits C<5:0> are provided. The first PMIN circuit 206 receives the characters W3~W0 and takes the smallest character as PMINVAL<15:0>. The first PMIN circuit 206 indicates the smallest character of the lower bit portion of the first bus ABUS and its corresponding position PMINLOC<1:0>. For example, if the minimum character is at ABUS<15:0>, then PMINLOC=00; if the smallest character is at ABUS<32:16>, then PMINLOC=01. Similarly, for the PMIN instruction, the characters W5 and W4 can be provided to the AH bus, and the characters W7~W5 can be provided to the BH bus for transmission to the second adder circuit 208. The second adder circuit 208 compares the character W4 with the characters W5~W7, and then compares the character W5 with the characters W6~W7, respectively, and then compares the character W6 with the character W7, respectively, according to Comparing the results, the corresponding comparison bits C<11:6> are provided. The second PMIN circuit 210 receives the characters W7 to W4, and takes the corresponding bit of the smallest character of the characters W7 to W4 as PMINVAL<31:16>. The second PMIN circuit 210 also indicates the corresponding position PMINLOC<3:2> of the smallest character located in the high-order portion of the first bus ABUS. For example, if the minimum character is at ABUS<79:64>, then PMINLOC=00; if the smallest character is at ABUS<95:65>, then PMINLOC=01. The high order/low order comparator circuit 212 compares the PMINVAL<15:0> characters with the PMINVAL<31:16> characters to identify which is the minimum value in ABUS<127:0>. The relative position of the minimum value MINLOC<2:0> can also be known by the comparison result of the high-order/low-order comparator circuit 212.

Referring to FIG. 2, for the PSAD instruction, the path selection circuit 202 (shown in FIG. 3) selects the byte A3 of the first operation element from the first bus ABUS by the selection of the byte. A0 is supplied to AL<31:0> and AH<31:0>, and provides AL<31:0> to the first adder circuit 204 and AH<31:0> to the second adder circuit 208, respectively. . The path selection circuit 202 takes the byte B6~B0 of the second operand from the second bus BBUS as BL<55:0> and transmits BL<55:0> to the first adder circuit 204. The path selection circuit 202 takes the byte B10~B4 of the second operand from the second bus BBUS as BH<55:0> and transfers BH<55:0> to the second adder circuit 208. For the PSAD instruction, the first adder circuit 204 divides the difference between the bytes A0 and B0, the difference between the bytes A1 and B1, the difference between the bytes A2 and B2, and the difference between the bytes A3 and B3. The difference is added together and provides the result of the first 10 bits PSAD<9:0>. The first adder circuit 204 adds the difference between the bytes A0 and B1, the difference between the bytes A1 and B2, the difference between the bytes A2 and B3, and the difference between the bytes A3 and B4. And provide the result of the second 10-bit PSAD<19:10>. The first adder circuit 204 adds the difference between the bytes A0 and B2, the difference between the bytes A1 and B3, the difference between the bytes A2 and B4, and the difference between the bytes A3 and B5. And provide the result of the third 10-bit PSAD<29:20>. The first adder circuit 204 adds the difference between the bytes A0 and B3, the difference between the bytes A1 and B4, the difference between the bytes A2 and B5, and the difference between the bytes A3 and B6. And provide the result of the third 10-bit PSAD<39:30>. By the same token, the second adder circuit 208 divides the difference between the bytes A0 and B4, the difference between the bytes A1 and B5, the difference between the bytes A2 and B6, and the difference between the bytes A3 and B7. Together, and provide the first 10-bit result PSAD<49:40>. The second adder circuit 208 sums the difference between the bytes A0 and B5, the difference between the bytes A1 and B6, the difference between the bytes A2 and B7, and the difference between the bytes A3 and B8. And provide the result of the second 10-bit PSAD<59:50>. The second adder circuit 208 sums the difference between the bytes A0 and B6, the difference between the bytes A1 and B7, the difference between the bytes A2 and B8, and the difference between the bytes A3 and B9. And provide the result of the third 10-bit PSAD<69:60>. The second adder circuit 208 sums the difference between the bytes A0 and B7, the difference between the bytes A1 and B8, the difference between the bytes A2 and B9, and the difference between the bytes A3 and B10. And provide the result of the fourth 10-bit PSAD<79:70>.

Figure 4 is an embodiment of a first adder circuit 204 of the present invention. The first adder circuit 204 processes the byte in AL<31:0> and BL<31:0> and provides PSAD<39:0> or C<5:0>. The first adder circuit 204 includes a difference circuit 402, a sum circuit 404, a selection logic 410, and a selection logic circuit 412. The difference circuit 402 has a plurality of difference units DIFF1 to DIFF8. The difference units DIFF1~DIFF8 are independent. The summing circuit 404 has summing units S1 to S4. The summation units S1 to S4 are independent of each other. Each difference unit judges the difference (no sign) between 4 bytes (ie, 2 pairs of bytes). Each difference unit inverts one of the bytes of each pair of bytes and then sums it with another. The difference produced by each pair of bytes is the absolute value of the error. The byte data received by the difference unit is determined by the instruction executed at the beginning. The selection logic circuit 410 has a complex multiplex circuit. Each multiplexed circuit is independent of each other. The multiplex circuits select a particular byte to the difference unit DIFF3 based on the instructions executed at the outset. As shown, for the PMIN instruction, when the control terminal of the selection logic circuit 410 is logic 1 (ie, the control code INSTR=1), the selection logic circuit 410 selects and outputs the byte BL<47:40>, BL. <31:24>, BL<39:32> and BL<23:16> to the difference unit DIFF3. The byte BL<47:40>, BL<31:24>, BL<39:32>, and BL<23:16> correspond to the byte groups A7~A4, respectively. For the PSAD instruction, when the control terminal of the selection logic circuit 410 is logic 0 (ie, the control code INSTR=0), the selection logic circuit 410 selects and outputs the byte groups BL<23:16>, AL<15:8>. , BL<15:8> and AL<7:0> to the difference unit DIFF3. The byte groups BL<23:16>, AL<15:8>, BL<15:8>, and AL<7:0> correspond to the byte groups B2, A1, B1, and A0, respectively. By the same token, for the PMIN instruction, when the control terminal of the selection logic circuit 412 is logic 1, the selection logic circuit 412 selects and outputs the byte groups AL<15:8> and AL<7:0> to the difference unit DIFF8. . The bytes AL<15:8> and AL<7:0> correspond to the byte groups A1 and A0, respectively. For the PSAD instruction, when the control terminal of the selection logic circuit 412 is logic 0, the selection logic circuit 412 selects and outputs the byte groups AL<23:16> and AL<15:8> to the difference unit DIFF3. The bytes AL<23:16> and AL<15:8> correspond to the byte groups A2 and A1, respectively.

For the PSAD instruction, the first inverting input of the difference unit DIFF1 receives the byte group BL<15:8>. The byte BL<15:8> corresponds to the byte B1. The second non-inverting input of the difference unit DIFF1 receives the byte AL<15:8>. The byte AL<15:8> corresponds to the byte A1. The difference unit DIFF1 determines the absolute value of the error (|A1-B1|) between the bytes A1 and B1. The difference unit DIFF1 takes the absolute value of the error (|A1-B1|) between the bytes A1 and B1 as the result AD1, and outputs it from the first output. Similarly, the third inverting input of the difference unit DIFF1 receives the byte group BL<7:0>. The byte BL<7:0> corresponds to the byte B0. The fourth non-inverting input of the difference unit DIFF1 receives the byte AL<7:0>. The byte AL<7:0> corresponds to the byte A0. The difference unit DIFF1 determines the absolute value of the error (|A0-B0|) between the bytes A0 and B0. The difference unit DIFF1 takes the absolute value of the error (|A0-B0|) between the bytes A0 and B0 as the result AD2, and outputs it from the second output. Similarly, the difference unit DIFF2 determines the absolute value of the error between the bytes A3 and B3 (|A3-B3|), and the absolute value of the error between the bytes A3 and B3 is taken as AD3, and is output by the first output. . The difference unit DIFF2 determines the absolute value of the error (|A2-B2|) between the bytes A2 and B2, and takes the absolute value of the error between the bytes A2 and B2 as AD4, and outputs it from the second output. In summary, when the control code INSTR is the PSAD command, the difference circuit 402 determines the absolute value of the error between the byte A0 and the byte B0~B3, and the error between the byte A1 and the byte B1~B4, respectively. The absolute value, the absolute value of the error between the byte A2 and the byte B2 to B5, and the absolute value of the error between the byte A3 and the byte B3 to B6, respectively.

The summation unit S1 calculates the total of the four bytes AD1 to AD4, and takes the calculated result as the 10-bit PSAD<9:0>. The calculation result of the summation unit S1 corresponds to (|A0-B0|)+(|A1-B1|)+(|A2-B2|)+(|A3-B3|). For the PSAD instruction, the difference unit DIFF3 determines the absolute value of the error between A0 and B1, and takes the absolute value of the error between A0 and B1 as AD6. The difference unit DIFF3 determines the absolute value of the error between A1 and B2, and takes the absolute value of the error between A1 and B2 as AD5. The difference unit DIFF4 determines the absolute value of the error between A2 and B3, and takes the absolute value of the error between A2 and B3 as AD8. The difference unit DIFF4 determines the absolute value of the error between A3 and B4, and takes the absolute value of the error between A3 and B4 as AD7. The sum unit S2 calculates the sum of the four bytes AD5 to AD8, and takes the calculated result as a 10-bit PSAD<19:10>. The calculation result of the summation unit S2 corresponds to (|A0-B1|)+(|A1-B2|)+(|A2-B3|)+(|A3-B4|). Similarly, for the PSAD instruction, the sum unit S3 calculates the sum of the four bytes AD9 to AD12, and takes the calculated result as the 10-bit PSAD<29:20>. The calculation result of the summation unit S3 corresponds to (|A0-B2|)+(|A1-B3|)+(|A2-B4|)+(|A3-B5|). Finally, for the PSAD instruction, the sum unit S4 calculates the sum of the four bytes AD13 to AD16, and takes the calculated result as the 10-bit PSAD<39:30>. The calculation result of the summation unit S3 corresponds to (|A0-B3|)+(|A1-B4|)+(|A2-B5|)+(|A3-B6|). Although FIG. 4 shows only one embodiment of the first adder circuit 204, the second adder circuit 208 is substantially similar to the first adder circuit 204 to determine that the byte A0 is associated with the byte B4~B7, respectively. The absolute value of the error, the absolute value of the error between the byte A1 and the byte B5~B8, the absolute value of the error between the byte A2 and the byte B6~B9, respectively, and the byte A3 The absolute value of the error between each bit and B7~B10. In addition, the second adder circuit 208 adds up to four absolute values of the error and provides four summed values based on the summed result. PSAD<79:40> contains these four totals.

In summary, for the PSAD instruction, the difference circuit 402 is used to determine each byte (A3: A0) in the first set of digits and each byte (B10: B0) in the second set of digits. The absolute value of the error. After the first group B3:B0 is processed, the comparison is started by the next higher bit, such as B1:B4, B2:B5, B3:B6...etc. Therefore, in eight groups, the absolute values of errors AD1~AD4, AD5~AD8, ..., AD29~AD32 will be generated. The summation circuit 404 sums the absolute values of the errors for each group and provides the corresponding sum of absolute values of the errors, PSAD<79:0>.

When the control code INSTR is a PMIN instruction, the difference circuit 402 is processed in substantially the same manner except for the selected bit groups. The sum of AD1~AD16 and PSAD<39:0> can be omitted, and only need to compare bits C<5:0>. The difference unit DIFF1 compares or otherwise determines the absolute value of the error between A1 and A3 and the absolute value of the error between A0 and A2. The first tuple A3 is the high tuple of the character W1, and the second tuple A1 is the high tuple of the character W0. The third byte A2 is the lower byte of the character W1, and the fourth byte A0 is the lower byte of the character W0. In the present embodiment, the difference unit DIFF1 compares the high byte and the low byte of the characters W1 and W0, respectively. The difference unit DIFF1 determines the comparison bit C<0>. Bit C<0> indicates which character (W1 or W0) is a smaller character. Similarly, the difference unit DIFF2 compares the high-order bytes A5 and A3 of the characters W2 and W1, and compares the lower bytes A4 and A2 of the characters W2 and W1 to determine which character (W2 or W1) is compared. Small characters and provide comparison bit C<3>. Similarly, the difference unit DIFF3 compares the high-order bytes A7 and A5 of the characters W3 and W2, and compares the lower bytes A6 and A4 of the characters W3 and W2 to determine which character (W3 or W2) is compared. Small characters and provide comparison bit C<5>. For the PMIN instruction, the difference unit DIFF4 can be omitted. The difference unit DIFF5 compares the upper bytes A5 and A1 of the characters W2 and W0, and the lower bytes A4 and A0 of the comparison characters W2 and W0 to determine which character (W2 or W0) is a smaller word. Yuan, and provide comparison bit C<1>. The difference unit DIFF6 compares the high-order bytes A7 and A3 of the characters W3 and W1, and the lower bytes A6 and A2 of the comparison characters W3 and W1 to determine which character (W3 or W1) is a smaller word. Yuan, and provide comparison bit C<4>. For PMIN, the difference unit DIFF7 can be omitted. The difference unit DIFF8 compares the high-order bytes A7 and A1 of the characters W3 and W0, and the lower bytes A6 and A0 of the comparison characters W3 and W0 to determine which character (W3 or W0) is a smaller word. Yuan, and provide the comparison bit C<2>.

In summary, for the PMIN instruction, the compare bit C<0> of the difference circuit 402 of the first adder circuit 204 represents the smaller of the characters W0 and W1. The comparison bit C<1> represents the smaller of the characters W0 and W2. The comparison bit C<2> represents the smaller of the characters W0 and W3. The comparison bit C<3> represents the smaller of the characters W1 and W2. The comparison bit C<4> represents the smaller of the characters W1 and W3. The comparison bit C<5> represents the smaller of the characters W2 and W3. Although FIG. 4 does not show the detailed circuit of the second adder circuit 208, the second adder circuit 208 also has the same difference circuit as the first adder circuit 204 for the character W4 of the higher order adder circuit 207. ~W8 performs the same comparison and provides the corresponding comparison bit C<11:6>. Thus, for PMIN, the compare bit C<6> represents the smaller of the characters W4 and W5. The compare bit C<7> represents the smaller of the characters W4 and W6. The compare bit C<8> represents the smaller of the characters W4 and W7. The comparison bit C<9> represents the smaller of the characters W5 and W6. The compare bit C<10> represents the smaller of the characters W5 and W7. The comparison bit C<11> represents the smaller of the characters W6 and W7. The first PMIN circuit 206 uses the compare bits C<5:0> to identify the smallest of the characters W0~W3. The second PMIN circuit 210 uses the comparison bit C<11:6> to identify the smallest of the characters W4~W7.

Figure 5 is an embodiment of the difference unit DIFF1 of the present invention. As shown, the difference unit DIFF1 has an adder pair. The adder pair has a high (or first) adder 502 and a low (or second) adder 504. Adders 502 and 504 each have an inverting input B and a non-inverting input A. Therefore, both the adder 502 and the adder 504 can perform a subtraction operation to determine the signal difference between the inverting input terminal B and the non-inverting input terminal A. For the PSAD instruction, the inverting input B of the adder 502 receives the byte B1. For the PMIN instruction, the inverting input B of the adder 502 receives the byte A3. For the PSAD and PMIN instructions, the non-inverting input A of adder 502 receives byte A1. The adder 502 inverts each bit of the byte received by the inverting input B to obtain an inverted value ~B, where ~ represents the inversion in the binary. The adder 502 performs the unsigned summation (ie, A+~B=AB) on the inverted result (~B) and the byte received by the input terminal A, and then adds the aggregated result to the output end. SUM output. Adder 502 has a carry out (CO) terminal CO for providing a carry output signal CO1. When the summation result obtained by the adder 502 overflows, the carry output signal CO1 is logic 1. The adder 502 also increments the summed result and outputs the incremented result from the output terminal INCSUM. The adder 502 has a parent output CP. If the adder outputs a carry input (not provided), the transfer output signal CP1 of the transfer output CP is logic 1. In Fig. 5, although there is no carry input, if the adder 502 receives and passes the carry input, the transfer output signal CP1 is logic 1. In one embodiment, each bit of the byte received by input A is OR-ORed with each bit of the byte received by input B. After the OR operation, you can get 8 results. Then, the AND operations are performed through the results of the eight operations. Based on the OR operation result and the AND operation result, the logical level of the transfer output signal CP1 of the transfer output terminal CP can be determined. The output terminal SUM is coupled to the input of the inverter 508. Inverter 508 has a separate inverter for each bit of the byte. The output of inverter 508 is coupled to input 0 of multiplexer 506. The output terminal INCSUM is coupled to the input terminal 1 of the multiplexer 506. The select input of multiplexer 506 receives carry output signal CO1. The output signal AD1 of the multiplexer 506 is the absolute value of the error between the bytes received by the inputs A and B of the multiplexer 502.

Similarly, for the PSAD instruction, the inverting input B of the adder 504 receives the byte B0. For the PMIN instruction, the inverting input B of the adder 504 receives the byte A2. For the PSAD and PMIN instructions, input A of adder 504 receives byte A0. The adder 504 inverts each bit of the byte received by the inverting input B to generate an opposite logical value, such as ~B. The adder 504 performs the unsigned summation of the inverted result (~B) and the byte received by the input terminal A, and provides an output signal to the output terminals INCSUM, SUM, and CO. Since the outputs INCSUM, SUM and CO of the adder 504 are similar to the adder 502, they will not be described again. The output CO of the adder 504 provides a carry output signal CO2. If the adder 504 has a transfer output CP, the transfer output CP can be omitted or omitted. The CP output of adder 504 may not output a signal. The output INCSUM of the adder 504 is coupled to the input 1 of the multiplexer 510. A multiplexer 510 is used to provide AD2. The output SUM of the adder 504 is coupled to the input of the inverter 512. The output of the inverter 512 is coupled to the input 0 of the multiplexer 510. The select input of multiplexer 510 receives carry output signal CO2. One of the two inputs of the AND gate 514 receives the carry output signal CO2. The OR gate 516 is used to generate a compare bit C<0>, and one of the two inputs of the OR gate 516 receives the carry output signal CO1. The output CP of the adder 502 is coupled to an input of the AND gate 514. The other input of the AND gate 514 receives the carry output signal CO2 of the output CO of the adder 504. The output of the AND gate 514 is coupled to the OR gate 516.

For the adders 502 and 504, if the byte of the input terminal A is larger than the byte of the input terminal B, the output terminal CO is logic 1, and the output terminal INCSUM indicates that the error between the input terminals A and B is absolute. The value, ie |AB|. When the adder 502 sets the carry output signal CO1 to logic 1, the compare bit C<0> output by the OR gate 516 is =1. When the carry output signal CO1 is logic 1, the bit values of the input terminals A and B may determine that the transfer output signal CP1 of the adder 502 is logic 0 or 1. When the carry output signal CO1 is logic 1, the OR gate 516 can set the compare bit C<0> to logic 1, and therefore, for the compare bit C<0>, the value of the output signal CP1 is not important. . For example, if the binary code received by input A is 00000100 (decimal code is 4), and the binary code received by input B is 00000010 (decimal code is 2), then between input terminals A and B. The difference is AB=00000010 (the decimal code is 2). The binary code received at input B will be inverted first, so the result after the inversion is ~B=11111101. When the binary code received at input A and ~B are summed with no sign, the summed result A+~B (or AB) is 00000001, and the carry output signal CO1 is logic 1 (transfer output signal CP1) =0). Therefore, the summed result (ie the value of the output SUM) is not the correct value. The output of the inverter (508 or 512) is ~SUM (ie, the inverse of the binary code of the output SUM) = 1111111. The value at the output of the inverter is also not the correct value. The value of the output INCSUM is 00000001+1=00000010, which is the correct value. Therefore, for the adders 502 and 504, when the byte of the input terminal A is larger than the byte of the input terminal B, the output terminal CO=1, and therefore, the corresponding multiplexer (506 or 510) will input. The value of end 1 (ie INCSUM) is considered the correct output (the absolute value between inputs A and B).

If the value of the input terminal A is less than or equal to the value of the input terminal B, the output terminal CO=0, and the corresponding multiplexer will treat the output signal ~B of the corresponding inverter (508 or 512) as correct. Output. When the value of input A is equal to the value of input B, the correct output is 00000000. Although the correct output will be reflected in the output terminals INCSUM and ~SUM, since the output terminal CO=0, the corresponding multiplexer will select ~SUM. When the value of the input terminal A is equal to the value of the input terminal B, the value of the delivery output terminal CP=1. For example, when the values of the input terminals A and B are both equal to 00001111, the value of the input terminal A plus the inverted value of the input terminal B is equal to 00001111 + 11110000 = 111111111 = SUM, and the value of the output terminal CP = 1. The inverted value of the output SUM (ie ~SUM) is 00000000, which is the correct value. The value of the output INCSUM is 1+11111111, and the result is 00000000, which is also the correct value (although it will not be selected by the multiplexer). When the value of input A is less than the value of input B, the output CO=0, and the multiplexer will treat ~SUM as the correct value. For example, if the value of input A is 00000010 and the value of input B is 00000100, then |A-B|=00000010. In this example, A+~B=00000010+11111011=11111101=SUM. Since the output CO=0, ~SUM=00000010 will be taken as the correct value. In this case, the value of the output INCSUM is equal to 1+11111101=11111111, which is not the correct value.

When the control code INSTR is the PSAD instruction, the adder 502 can obtain the error absolute value AD1=|A1-B1| according to the PSAD operation, and the adder 504 can obtain the error absolute value AD2=|A0-B0|, and the comparison can be omitted. Bit C<0>. When the control code INSTR is the PMIN instruction, if A1>A3, the high byte of the character W0 is larger than the high byte of the character W1, so W0>W1. In this example, when W0>W1, since CO1=1, C<0>=1. When A3>A1, both CO1 and CP1 of adder 502 are logic 0, so C<0>=0 is used to represent character W0<W1. If A1 = A3, the output of adder 502 is CO1 = 1 and CP1 = 0. In this example, the result of the comparison of the lower bytes of the relative character of adder 504 is used to determine the relative values of characters W0 and W1. When the high-order tuples are equal, CP1=1, and if A0>A2, the lower byte of the character W0 is larger than the lower byte of the character W1, so W0>W1. In this example, both CP1 and CO2 are logic 1, so C<0>=1. If the high-order tuples are equal, then CP1=1, then A0 is less than or equal to A2, so CO2 is logic 0, so that C<0>=0. In this example, the character W0 is less than or equal to W1, and in other examples, the character W0 is taken as the minimum value. The other difference circuits (DIFF2~DIFF8) have the same structure and operation to judge AD3~AD16. The difference units DIFF4 and DIFF7 can be simplified. In particular, it is not necessary to receive the CO and CP to determine the logical device of the corresponding compare bit C<x>. The transfer logic used by each individual adder can also be omitted if necessary.

Please refer to Figures 4 and 5. In the PMIN instruction and the PSAD instruction, the same adder circuit is used. In particular, each adder pair in each difference unit can be applied to the PMIN instruction and the PSAD instruction. For the PSAD instruction, each individual adder circuit is used to obtain the absolute value of the error between the input byte pairs. For the PMIN instruction, although the sum of the absolute values of the errors obtained by the PSAD instruction is not necessary, each adder pair uses a comparison between the bits to determine which character has the smallest value. In the PSAD instruction, the path selection circuit maximizes the adder to aid the PMIN instruction. As mentioned above, for the PMIN instruction, multiple adders are divided into a number of adder pairs. Providing a high portion (eg, a high byte) of a pair of digital code (eg, a high byte) to a corresponding input of the first adder, and providing the lower portion of the log code (eg, a low byte) to the first The corresponding input of the two adders. By modifying the two adders, they get the carry output. The high adder in the adder pair has a transfer output. The carry output and the pass output of each adder pair are used to determine the minimum value of each digit code pair. For the PSAD instruction, the result of the adder processing is used to obtain the absolute value of the error between the first operand and the second operand, and for the PMIN instruction, the result of the adder processing can obtain 8 characters. The smallest of the sets, where the first operand has 4 bytes and the second operand has 11 bytes.

Figure 6 shows a possible embodiment of the summation unit S1 of the present invention. The summing unit S1 has an adder 602, an adder 604, and an adder 606 for providing a result PSAD<9:0> having 10 bits. The adder 602 and the adder 604 each have 8 bits, and the adder 606 has 9 bits. The adder 602 and the adder 604 are similar to the adder 502 except that the adder 602 and the adder 604 do not have an inverting input, and the INCSUM circuit is not necessary and can be omitted. In addition, the transmission output circuit is not necessary and can be omitted. The adder 602 performs sign-free summation for the binary values AD1 and AD2, and provides a first sum value SUM1 (= AD1 + AD2) and a corresponding carry output C1. The adder 604 performs an unsigned addition on the binary values AD3 and AD4, and provides a second sum value SUM2 (= AD3 + AD4) and a corresponding carry output C2. The carry output C1 is taken as the most significant bit (MSB) of SUM1. The carry output C2 is taken as the most significant bit (MSB) of SUM2. The first input of the adder 606 receives the result of combining the carry output C1 and the first sum value SUM1. The second input of the adder 606 receives the combined result of the carry output C2 and the second sum value SUM2. Both inputs of adder 606 receive 9 bits. The adder 606 performs unsigned addition on the data (C1, SUM1+C2, SUM2) received at the two inputs, and provides an output result PSAD<9:0> having 10 bits. The smallest 9-bit PSAD<8:0> represents the result of the unsigned binary summation, and the most significant bit MSB PSAD<9> represents the summed result of the carry output. In this embodiment, the summation unit S1 adds the first error absolute value group (AD1~AD4) to obtain the first error absolute value sum PSAD<9:0>. The other summation units S2~S4 have the same structure, and the total error absolute value groups AD5~AD8, AD9~AD12 and AD13~AD16 are respectively used to provide the absolute sum of errors PSAD<19:10>, PSAD<29. :20> and PSAD<39:30>.

Figure 7 is an embodiment of a PMIN circuit 206 of the present invention. The PMIN circuit 206 has a decode logic circuit 701, a select logic circuit 728, and a location logic 703. The decoding logic circuit 701 has an inverter 702, an inverter 704, an inverter 706, an inverter 712, an inverter 714, an inverter 720, an inverter 710, an inverter 718, and an inverter 724, and AND gate 708, AND gate 716, AND gate 722 and AND gate 726. The AND gate 708, the AND gate 716, the AND gate 722, and the AND gate 726 each have three inputs. The position logic circuit 703 has an OR gate 730 and an OR gate 732. Both the OR gate 730 and the OR gate 732 have two inputs. Comparison bits C<2:0> are provided to inverter 702, inverter 704, and inverter 706, respectively. The AND gate 708 receives the outputs of the inverter 702, the inverter 704, and the inverter 706. The AND gate 708 outputs a signal W0_MIN. When the character W0 is the smallest character, the signal W0_MIN is logic 1. The compare bits C<3:4> are supplied to the inverter 712 and the inverter 714, respectively. The three inputs of the AND gate 716 receive the outputs of the inverter 712 and the inverter 714, respectively, and compare bits C<0>. The AND gate 716 outputs a signal W1_MIN. When the character W1 is the smallest character, the signal W1_MIN is logic 1. The input of inverter 720 receives C<5>. The AND gate 722 receives the output of the inverter 720, C<1> and C<3>, respectively. The AND gate 722 outputs a signal W2_MIN. When character W2 is the smallest character, signal W2_MIN is a logic one. Inverters 710, 718 and inverter 724 receive signals W0_MIN, W1_MIN, and W2_MIN, respectively, for generating signals ~W0_MIN, ~W1_MIN, and ~W2_MIN, respectively. The signals ~W0_MIN, ~W1_MIN, and ~W2_MIN indicate that the corresponding character is not the minimum value, respectively. The AND gate 726 receives signals ~W0_MIN, ~W1_MIN, and ~W2_MIN, and outputs a signal W3_MIN. When character W3 is the smallest character, signal W3_MIN is a logic one.

AL<15:0>, BL<15:0>, BL<31:16>, and BL<47:32> represent the characters W0~W3, respectively. Selection circuit 728 receives AL<15:0>, BL<15:0>, BL<31:16>, BL<47:32>, and signals W0_MIN~W3_MIN. At the same time, only one of the signals W0_MIN~W3_MIN is logic 1, which means that the corresponding character of W0_MIN~W3_MIN is the minimum value during this period. Therefore, the selection circuit 728 takes one of the characters W0 to W3 as the minimum character and outputs the minimum character as PMINVAL<15:0>. The OR gate 730 receives the signals W3_MIN and W2_MIN. The OR gate 730 has an output for outputting the corresponding position bit PMINCLOC<1>. The OR gate 732 receives the signals W3_MIN and W1_MIN. The OR gate 732 has an output for outputting the corresponding position bit PMINCLOC<0>. In the present embodiment, the smallest one of the characters W0 to W3 is known by PMINVAL<15:0>, and PMINLOC<1:0> indicates the first bus ABUS received by the low-order adder circuit 203. The corresponding position of the smallest character in the second half of the character. The PMIN circuit 210 is similar in construction to the PMIN circuit 206 for providing PMINVAL<31:16> and PMINLOC<3:2> which represent the smallest of the characters W4~W7. PMINLOC<3:2> indicates the corresponding position of the smallest of the first half of the first bus of the first bus ABUS received by the high-order adding circuit 207.

Figure 8 is an embodiment of a high order/low order comparison circuit 212 of the present invention. The inverting input of the 16-bit comparison circuit 802 receives the PMINVAL<31:16> provided by the high-order adder 207. The non-inverting input of comparison circuit 802 receives PMINVAL<15:0> provided by low-order adder circuit 203. Comparison circuit 802 has a carry output CO for providing a signal MINLOC<2>. The comparison circuit 802 compares the high-order and low-order minimum characters and takes the carry output as MINLOC<2>. The carry-out terminal CO of the comparison circuit 802 is identical to the output CO of the adder described above. If the character of PMINVAL<15:0> is greater than the character of PMINVAL<31:16>, then MINLOC<2> of the carry output terminal CO of the comparison circuit 802 is logic 1, otherwise MINLOC<2> is logic 0. MINLOC<2> is the most significant bit (MSB) of the position value MINLOC<2:0>. Since MINLOC<2> is a logic 1, the minimum value is in the first half of the first bus ABUS. Conversely, if MINLOC<2> is a logic 0, it means that the minimum value is in the second half of the first bus ABUS. MINLOC<2> serves as a selection input for multiplexer 804, multiplexer 806, and multiplexer 808, and multiplexer 804 selects the byte value PMINVAL<23:16> or PMINVAL<7:0> as the lower bit. Group MINVAL<7:0>. The bit value PMINVAL<23:16> or PMINVAL<7:0> represents the low byte of the smallest character found from the high and low order portions. The multiplexer 806 selects the byte value PMINVAL<31:24> or PMINVAL<15:8> as the high byte MINVAL<15:8>. PMINVAL<31:24> or PMINVAL<15:8> represents the high byte of the smallest character found from the high and low order parts. The multiplexer 808 selects the location bits PMINLOC<3:2> or PMINLOC<1:0> as MINLOC<1:0>. The location bits PMINLOC<3:2> or PMINLOC<1:0> represent the least significant location bits of the higher or lower order portion. As described above, the comparison circuit 802 can determine the most significant bit of MINLOC or MINLOC<2>. Therefore, MINLOC<2:0> indicates the location of the smallest character of the first row ABUS.

Although many preferred embodiments have been described in detail herein, other possible variations have also been considered. For example, all of the circuits described above can be implemented using any logic device or logic circuit. The functions of the above logic circuits can also be realized by using software or firmware in the integrated device. The above described circuit may have a number of inverting means for providing positive or negative logic for any signal. The circuit disclosed in the present invention uses a digital code or a binary byte or a character, but does not limit the number of bits of a digital code or a binary code. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

100. . . microprocessor

102. . . Scheduler

104. . . Complex integer execution unit

106. . . Simple integer execution unit

108. . . Floating point execution unit

110. . . Media unit

114, 802. . . Comparison circuit

112. . . Other unit

202. . . Path selection circuit

203. . . Low order adder circuit

204. . . First adder circuit

206. . . First PMIN circuit

207. . . High order adder circuit

208. . . Second adder circuit

210. . . Second PMIN circuit

212. . . High order/low order comparator circuit

302. . . Buffer circuit

304, 306, 308, 506, 510, 804, 806, 808. . . Multiplexer

402‧‧‧Differential circuit

404‧‧‧sum circuit

410, 412‧‧‧Select logic circuit

502, 504, 602, 604, 606‧‧ ‧ adders

514, 708, 716, 722, 726‧‧‧AND gate

516‧‧‧OR gate

508, 512, 702, 704, 706, 712, 714, 720, 710, 718, 724‧‧ ‧ inverter

728‧‧‧Selection circuit

DIFF1~DIFF8‧‧‧Differentiation unit

S1~S4‧‧‧sum unit

FIG. 1 shows an embodiment of a microprocessor 100.

Figure 2 is an embodiment of a comparison circuit.

Figure 3 is an embodiment of the path selection circuit of the present invention.

Figure 4 is an embodiment of the first adder circuit of the present invention.

Figure 5 is an embodiment of the difference unit DIFF1 of the present invention.

Fig. 6 shows an embodiment of the sum unit S1 of the present invention.

Figure 7 is an embodiment of a PMIN circuit 206 of the present invention.

Figure 8 is an embodiment of a high order/low order comparison circuit 212 of the present invention.

202. . . Path selection circuit

203. . . Low order adder circuit

204. . . First adder circuit

206. . . First PMIN circuit

207. . . High order adder circuit

208. . . Second adder circuit

210. . . Second PMIN circuit

212. . . High order/low order comparator circuit

Claims (39)

a judging system for finding a minimum binary code from at least two binary codes, the judging system comprising: a first adder, adding a plurality of first bits and a plurality of second bits to provide a a first carry output and a first pass output, wherein the first bit is a high bit of a first binary code, and the second bit is inverted to a high bit of a second binary code a second adder, adding a plurality of third bits and a plurality of fourth bits for providing a second carry output, wherein the third bit is a lower bit of the first binary code, Waiting for the fourth bit to be inverted to the lower bit of the second binary code; and a comparison circuit determining whether the first binary is based on the first carry output and the second carry output and the first transfer output The code is greater than the second binary code. The judging system of claim 1, wherein the first binary code and the second binary code have no sign. The judging system of claim 1, wherein the first adder and the second adder perform an unsigned binary addition. The judging system of claim 1, wherein the first binary code and the second binary code are a first unsigned binary character and a second unsigned binary character, respectively. The first adder compares the high-order tuple of the first unsigned binary character and the second unsigned binary character, and the second adder compares the first unsigned binary character with the second unsigned sign The lower byte of a binary character. The judgment system described in claim 1, wherein the first The pass output represents whether the first adder receives an incoming input. The judging system of claim 1, wherein the first bit and the second bit are ORed one-to-one, and the result of the OR operation is ANDed, according to an OR operation. The result and the AND operation result determine the first delivery output. The judging system of claim 1, wherein the comparing circuit comprises: an OR gate having a first input end, a second input end, and a first output end, the first input end receiving the first a carry output, the level of the output indicates whether the first binary code is greater than the second binary code; and an AND gate having a third input terminal, a fourth input terminal, and a second output terminal The third input receives the first transfer output, the fourth input receives the second carry output, and the second output is coupled to the second input. A judging system for quickly finding a horizontal minimum value from a plurality of digital code codes, the judging system comprising: a complex difference circuit, each difference circuit comparing a first digital bit code and a second digital bit code, wherein each A difference circuit includes: a high adder for comparing a high portion of the first digit code and a high portion of the second digit code to provide a first carry output and a transfer output; and a low adder, Comparing a low portion of the first digit code and a low portion of the second digit code to provide a second carry output; a comparison circuit for comparing the first carry output and the second carry output and comparing the transfer outputs for learning one of the lowest digit codes of the digital code; and a path selection circuit for the digital bits Each of the codes is assigned to at least one of the high adder and the low adder for comparing each digit code with another digit code. The judging system of claim 8, wherein the comparing circuit comprises: a first comparing circuit, comparing the first carry output, the second carry output and the transfer output of each difference circuit for providing a plurality of comparison bits; and a second comparison circuit for learning the minimum number of the digits based on the comparison bits. The judging system of claim 9, wherein the first comparison circuit of each difference circuit comprises an AND gate and an OR gate, the AND gate comparing the transmission output with the second carry output, To generate a first bit, the OR gate compares the first bit with the first carry output to provide one of the compare bits. The judging system of claim 9, wherein the second comparison circuit decodes the comparison bits to provide a plurality of minimum bits, each of the minimum bits representing each of the digits Whether a digit code is the minimum value. The judging system of claim 8, wherein the digit code comprises an unsigned binary character, and a high portion of each digit code of the digit code has a high byte, each of the digit codes One digit code The lower portion has a lower byte of a corresponding digital code. The judging system of claim 8, wherein the high adder of each difference circuit and the low adder perform an unsigned binary addition. The judging system of claim 8, wherein each of the transfer outputs represents a carry-in of a high adder of one of the difference circuits. The judging system of claim 8, wherein the digit code is stored in a memory, the judging system further comprising a position circuit for determining a memory location of the minimum digit code of the digit code . The judging system of claim 9, further comprising: a memory for storing the digit code, wherein the second comparison circuit comprises a decoding circuit for decoding the comparison bit for Providing a plurality of minimum bits; a selection circuit, using the minimum bits, selecting one of the digit codes stored in the memory as the minimum digit code; and a position circuit according to the minimum bits A position value is provided, the position value indicating the position of the least digit code in the memory. A judging method for finding one of the plurality of digit codes, the judging method comprising the steps of: comparing a high bit of a first digit code with a high bit of a second digit code to provide a first a carry output and a pass output; comparing a lower bit of the first bit code and a lower bit of the second bit code to provide a second carry output; and determining according to the first and second carry outputs and the transfer output Out of The first digit code or the second digit code is a smaller code. The method for judging according to claim 17 further includes: comparing each of the adder pairs of the plurality of adder pairs, comparing the upper bits of the first digit code with the high bits of the second digit code, and comparing the first a lower bit of a digit code and a lower bit of the second digit code and determining that the first digit code or the second digit code is the smaller code; transmitting each digit code of the digit code to the addition At least one adder pair of the pair of cells is used to compare each digit code with another digit code; and based on the compared result, one of the digit codes is known as the least digit code. The method for determining a method according to claim 18, wherein a plurality of comparison bits are generated by combining a complex carry output and a complex transfer output, and by decoding the comparison bits, the digital code can be determined. The minimum digit code. The method of judging according to claim 18, further comprising: determining a position of the minimum digit code among the digit codes stored in a memory in the memory. A judging system for performing one of a horizontal minimum command and an error absolute value sum command using a common adder circuit, the judging system comprising: a complex digital code, the absolute value sum instruction for the error, the digital code The first digital code set includes a second digital code set, and the second digital code set includes a complex digital code pair, each digital code pair having a high digital code and a low digital code; a complex adder, each adder compares a first digit code with a second digit code to provide an absolute value of the error, a carry output and a transfer output; and a total circuit, summing the absolute errors a value for providing a complex error absolute value plus a total value; a comparison circuit combining the carry output and the transfer output to find a minimum digit code pair of the digit code pairs; and a path selection circuit, When performing the horizontal minimum instruction, the path selection circuit transmits each digital code pair of the digital code pair to at least one adder pair of the adders for using each digital code pair with other digital code Comparing, when the error absolute value sum command is executed, the path selection circuit transmits the first digit code set and the second digit code set to the adders for learning each of the first digit code sets An absolute value of the error between a digit code and each digit code of the second digit code set, the second digit code set having a continuous digit code. The judging system of claim 21, wherein the path selecting circuit executes the first sum code set and the second digit code set by a first bus bar and a first The two bus bars are respectively sent to a third bus bar and a fourth bus bar. When the minimum level command is executed, the path selecting circuit transmits the digit code pair from the first bus bar to the third bus bar. Row and fourth bus. The judging system of claim 21, wherein the path selection circuit transmits each digit code of the first digit code set to one of the adders when the error absolute sum command is executed a first adder of the adder pair and each digit of the second digit code set The code is passed to one of the first adder pairs of the adders. The judging system of claim 23, wherein the first adder provides an absolute value of the error to the first adder. The judging system of claim 21, wherein the summing circuit comprises: a first adder, adding a first error absolute value pair provided by one of the first adder pairs of the adders And a second adder, adding a second error absolute value pair provided by one of the second adders of the adders to provide a second sum total a third adder that sums the first summed value and the second summed value to provide a sum of absolute values of the errors. The judging system of claim 25, wherein the first and second adder pairs each comprise: a high adder, a high digit code pair and a second digit code pair of a first digit code pair Comparing one of the high digitizers, the high adder provides the pass output; and a low adder comparing the low digit code of the first digit code pair with the low digit code of the second digit code pair . The judging system of claim 21, wherein when the error absolute value sum instruction is executed, each digit code of the digit code comprises an unsigned bit group, when the horizontal minimum instruction is executed Each of the digit codes includes an unsigned character. The judging system of claim 21, wherein each of the pass outputs indicates whether a carry input is incremented by a high adder of an adder pair of the adders. The judging system of claim 21, wherein the comparing circuit comprises: a first comparing circuit, the carry output of each adder pair of the adders is combined with the transfer output, Generating a comparison bit; and a second comparison circuit determining a minimum number bit pair of the plurality of bit pairs based on the comparison bits. The judging system of claim 29, wherein the first comparison circuit of each adder pair of the adders has an AND gate and an OR gate, the AND gate will be a high adder The pass output is combined with a pass output of a low adder for generating a first bit, the OR gate correlating the first bit with a carry output of the high adder to provide a compare bit yuan. The judging system of claim 29, wherein the second comparing circuit decodes the comparing bits to provide a complex minimum bit, each minimum bit representing each digit of the pair of digits Whether it is a minimum digit code pair. The judging system of claim 29, further comprising: a memory for storing the digit code pairs, the second comparison circuit comprising a decoding circuit, the decoding circuit decoding the comparison bits for providing a plurality of minimum bits; a selection circuit that selects one of the digit code pairs and, based on the minimum bits, the selected pair of digits as a minimum digit pair, and the least digit code Storing in the memory; and a position circuit providing a position value based on the minimum bits, The position value indicates the position of the smallest digit code pair in the memory. A judging method for performing a horizontal minimum instruction and an error absolute value summation instruction by using a common adder circuit, the determining method comprising: receiving a complex digital code, and when performing the error absolute value sum instruction, the digital The code includes a first digit code set and a second digit code set. When the horizontal minimum instruction is executed, the digital code includes a high digit code and a low digit code; a complex adder is provided, and each adder will Comparing the first digit code with a second digit code for providing an absolute value of the error and a carry output; summing the absolute values of the errors to provide a sum of absolute values of the complex errors; classifying the adders into a plurality of adder pairs and providing a pass output; combining the carry outputs and the pass outputs for knowing a minimum number of bits of the digital code; and when performing the horizontal minimum command, the digital code Each digit code is transmitted to at least one adder pair of the pair of adders for comparing each digit code with another digit code, and performing the error And transmitting, by the summation instruction, the first digit code set and the second digit code set to the adder pair, to learn each digit code of the first digit code set and each of the second digit code set The absolute value of the error between consecutive digit codes. The method for judging according to claim 33, wherein when the absolute value summation instruction is executed, the method further comprises: Transmitting each digit code of the first digit code set to a first adder of a first adder pair of the adder; transmitting each digit code of the second digit code set to the adder a second adder of the first adder pair. The method for determining a method according to claim 33, wherein the summing step comprises: adding a pair of first error absolute values provided by the first adder pair of the adder pair to generate a first Adding a total value; summing the pair of absolute values of the second adder pair provided by the adder pair to generate a second summed value; and summing the first summed value and The second summed value is used to provide a sum of absolute values of the errors. The method of claim 33, wherein the step of providing and classifying the adders comprises: comparing a first adder by a high adder of each adder pair a high digit code of the digit code pair and a high digit code of a second digit code pair for providing a first carry output and the pass output; comparing the low adder of each adder pair A low digit code of the first digit code pair and a low digit code of the second digit code pair are used to provide a second carry output. The judging method of claim 33, wherein the combining step comprises: a first carry output and a second carry output of each adder pair of the adder pair and one of the transfer outputs Combined to provide a comparison bit; and, based on the comparison bits, a minimum number of bits of the digital code. The method of claim 37, wherein the step of learning the minimum digit code of the digit code comprises: decoding the comparison bits to provide a complex minimum bit, each minimum bit representing Whether the corresponding digital code is the minimum digital code. The method for determining a method according to claim 38, further comprising: storing the digital code in a memory; and finding, according to the minimum bits, the minimum digit code of the digital code in the memory The position in the body.