JPS6174050A - Priority rank determining system for right of using bus - Google Patents

Abstract

PURPOSE:To determine a priority rank for a right of using a bus of a number of bus masters by inputting competition arbitrated bus using requests to bus arbiters and outputting them to a priority determining circuit. CONSTITUTION:A priority rank of bus using requests of plural bus masters (1-1)-(1-4)...,(16-1)-(16-4) directly connected to memory access controllers 41-56 is directly arbitrated at first. The arbitrated bus using requests are inputted to bus arbiters 21-36 and outputted to a priority determining circuit 17. A competitive arbitration of the bus using requests is done by a priority rank of direct memory access request input terminals to which bus using request lines of direct memory access controllers 41-56 and the competition arbitrated bus using requests are inputted to the bus arbiters 21-36.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is applicable to bus use rights in a multipath system having a large number of bus masters, such as a device that connects to multiple lines and analyzes information. (Regarding improvement of the rank determination method.

In a multi-path system in which a large number of bus masters (processing circuits that permit use of the bus) are connected to one bus, it is necessary to determine the priority order of bus use rights among the large number of bus masters. It is desirable to be able to connect as many bus masters as possible and to determine the priority order of the right to use these buses.

[Conventional technology]

FIG. 2 is a block diagram of a conventional bus use right priority determining circuit.

In the figure, 1 to 16 are path masters, 17 is a priority determination circuit, and 21 to 36 are bus arbiters (bus arbitration circuits), with the smaller number having a higher priority.

To explain the operation, for example, when a bus use request signal is input from the bus use request line of the bus master 1 with the highest priority to the terminal S that accepts the bus use request of the bus arbiter 21, the terminal BR that requests the bus use right of the bus arbiter 21 is inputted.
The EQ outputs a signal requesting the right to use the bus to the priority determining circuit 17.

As a result, the priority determination circuit 17, which knows the priorities of the bus arbiters in advance,
Since this has the highest priority, a bus use permission signal is manually input to the bus priority input terminal BPRN of the bus arbiter 21.

Since the bus arbiter 21 has obtained permission to use the bus, the bus arbiter 21 notifies the path master 1 via the bus permission line from the terminal AEN, which notifies bus permission, that it has obtained permission to use the bus, and also from the terminal BUSY, which indicates that the bus is in use. is notified to the bus arbiters 2 to 36.

At this time, when a bus request signal is input from the bus use request line of the bus master 2 to the terminal S that accepts the bus use request of the bus arbiter 22, a signal requesting the bus use right is sent from the terminal BREQ of the bus arbiter 22, which requests the bus use right. is output to the priority determining circuit 17, and a signal requesting bus use is output from the terminal CBRQ indicating that the bus arbiter with a lower priority is requesting the use of the bus, and waits for bus master 1 to finish using the bus. .

The bus arbiter 21 learns that there is a bus use request from a bus arbiter with a lower priority, and when the bus master I finishes using the bus, the bus arbiter 21 abandons the bus use request.

As a result, the priority determination circuit 17 determines whether the bus priority determination circuit 17 determines whether the bus priority determination circuit 17
Outputs a bus use permission signal to

Since the bus arbiter 22 has obtained permission to use the bus, the bus arbiter 22 notifies the bus master 2 from the terminal AEN that it has obtained permission to use the bus, and also sends a signal to the bus arbiter 1 from the terminal BUS'Y indicating that the bus is in use. Notify 36 that the bus is in use.

At this time, a signal from the bus use request line of the bus master 1 to the bus use request line is input to the terminal S that accepts the bus use request of the bus arbiter 21, and then the bus use right is received from the terminal BREQ of the bus arbiter 2I that requests the bus use right. The requested signal is output to the bryo-rich determination circuit 17.

Since the priority of the bus arbiter 21 is higher than that of the bus arbiter 22, the priority determination circuit 17 sends the bus use permission signal to terminal B of the bus priority input of the bus arbiter 21 even when the bus master 2 is using the bus.
Manpower the PRN.

Since the bus arbiter 21 has obtained permission to use the bus, it notifies the bus master 1 via the bus permission line from the terminal AEN, which notifies bus permission, that it has obtained permission to use the bus. Notify the bus arbiters 2 to 36 that the bus is in use.

In this way, the right to use the bus for bus masks 1 to 16 is arbitrated according to the priority order.

[Problem that the invention seeks to solve]

However, if the frequency of the synchronized clock signal of the bus is LOMHz, which is currently the highest frequency, the delay time of the priority determination circuit 17 from the bus arbiter issuing a bus use request to granting bus use permission, Even if one bus arbiter is used for each bus mask and connected in parallel as shown in FIG. 2, there is a problem that only a maximum of 16 bus arbiters can be used.

[Means for solving problems]

The problem described above is that the bus use request line and path use permission line of each of the plurality of path masks are connected to the direct memory access request input terminal (DREQ) and the direct memory access permission output terminal (DREQ) of the direct memory access controller set in cascade mode. DACK), and outputs the contention-arbitrated bus use request signal to the bold request signal output terminal (H
RQ), and is input to the terminal (S) that accepts the bus use request from the bus arbiter, and the bus use permission signal from the terminal (AEN) that notifies the bus use permission from the bus arbiter is sent to the direct memory access. The controller's input terminal for receiving the path use permission signal (
This problem can be solved by the bus use right priority determining system of the present invention, in which a plurality of bus arbiters connected in this way are connected in parallel.

[Effect]

According to the present invention, the direct memory access controller first arbitrates the priorities of the bus usage requests of a plurality of bus masters connected to the direct memory access controller, and the bus arbiter manually selects the arbitrated bus usage requests. Since the signal is output to the priority determination circuit, it is possible to determine the priority order of bus usage rights for 16 or more bus masks even if the frequency of the bus synchronization clock signal is currently the highest 10 MHz.

〔Example〕

FIG. 1 is a block diagram of a bus use right priority determining circuit according to an embodiment of the present invention.

In the figure, 1-1 to 1-4, 16-1 to 16-4 are bus masks, 41.56 is a direct memory access controller, and bus masters 1-1 to 1-4 are connected to the bus arbiter 21 with the highest priority. The bus master 16-
1 to 16-4 are connected to the 16th direct memory access controller 56, which is connected to the bus arbiter 36 with the lowest priority. Although not shown in the figure, the bus arbiters 22, 23, etc. also have the bus arbiters 21, 3.
6, a direct memory access controller and a bus mask are connected. The same reference numerals indicate the same functions throughout the figures.

The difference between FIG. 1 and FIG. 2 is that the bus request lines and bus permission lines of each of the four bus masks are set to cascade mode, which is used to control priorities.
Direct memory access controllers 41 to 56 are connected to direct memory access request input terminals D-REQI to DREQ4 and direct memory access permission output terminals DACK 1 to DACK 4 of priorities 1 to 4, respectively. The controller is generally DREQ, DA
A bus use request signal whose priorities have been arbitrated by competition (4 sets of CK terminals) is output from the hold request signal output terminal IRQ, inputted to the terminal S for accepting bus use requests from the bus arbiters 21 to 36, and inputted to the bus arbiter 2
The terminal AEN for notifying permission to use the buses 1 to 36 is directly connected to the input terminal HLDA of the memory access controllers 41 to 56 for receiving a bus use permission signal.

In this way, for example, contention arbitration of bus use requests of bus masters 1-1 to 1-4 can be performed by direct memory access controller 41 to the direct memory connected to the bus use request lines of bus masters 1-1 to 1-4. Access request input terminal DR
This is done based on the EQ priority, and this conflict-arbitrated bus use request is sent to the bus arbiter 21 and output to the priority determination circuit 17, so even if the frequency of the bus synchronization clock signal is currently the highest, 10 MHz, Priority determination of bus usage rights can be performed with respect to a 16×4 bus mask.

〔Effect of the invention〕

As described in detail above, according to the present invention, it is possible to determine the priority order of bus use rights for a larger number of bus masks than in the past.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a bus usage right priority determination circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram of a conventional bus usage right priority determination circuit. In the figure, 1 to 16.1-1 to 1-4. 16-1 to 16-4 are bus masks, 17 is a priority determination circuit, 21 to 36 are bus arbiters, and 41 to 56 are direct memory access controllers.

Claims (1)

[Claims] In a multi-bus system, the bus use request line and bus use permission line of each of a plurality of bus masters are connected to the direct memory access request input terminal (DREQ) and direct memory access permission output terminal (DREQ) of a direct memory access controller set to cascade mode. DACK), the contention-arbitrated bus use request signal is output from the hold request signal output terminal (HRQ), and inputted to the bus arbiter's bus use request acceptance terminal (S);
A terminal (A) that notifies permission to use the bus from the bus arbiter.
The bus use permission signal from EN) is input to the input terminal (HLDA) of the direct memory access controller for receiving the bus use permission signal, and a plurality of bus arbiters connected in this way are connected in parallel. A priority determination method for bus usage rights characterized by: