JPH10289203A - Bus arbitrating device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To secure service quality in consideration of respective device characteristics by allowing a device which has a transfer quantity counter value smaller than a reference counter value to use a bus when there are devices which have transfer counter values larger and smaller than the reference counter value based upon a clock respectively. SOLUTION: Comparing means 13-1 to 13-n provided for devices 3-1 to 3-n compare transfer data counters 12-1 to 12-n with reference counters 11-1 to 11-n and output whether actual transfer is delayed or precedent to an allocation determining means 10. Then the allocation determining means 10 allows a device which has a transfer quantity counter value smaller than the value of a reference counter to use the bus when there are devices having values of the transfer data counters 12-1 to 12-n smaller and larger than the values of the reference counters 11-1 to 11-n.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus system used for a personal computer.

[0002]

2. Description of the Related Art In recent information processing apparatuses, a bus method is generally used as a method of transferring data between connected devices.
In particular, a PCI bus is a standard for personal computers.

In general, in data transfer by bus connection, when there are transfer requests from a plurality of devices, the order of transfer is controlled by a bus arbiter in order to prevent data collision on the bus. The bus arbitrator monitors the bus as shown in FIG.
When (REQ1 to REQn) are input, the transfer permission signal 102 (GNT1 to GNT) is determined according to the determined arbitration method.
n) is output to the device. FIG. 3 shows a case where the number of devices is n.

In a bus arbitration device, when a transfer request is received from a plurality of devices at the same time, it is necessary to use only one device using the bus during a given time, and it is necessary to determine some arbitration method. . Intel's 82437F as a standard control device for the PCI bus
Although there is an X-PCIset (hereinafter, i82437FX), the bus arbitration device of the i82437FX employs a fixed priority scheme and a round robin scheme.

[0005] The fixed priority method is a method in which a priority is determined for each device, and when there are a plurality of requests, transfer is permitted to the device with the highest priority.

[0006] The round robin method is a method in which devices are circulated to determine an order, and transfer permission is equally given to each device.

In the PCI bus, the time for which a device to which transfer permission is given occupies the bus, that is, the data transfer length and transfer time, are determined by each device, and there is no limit.
Therefore, it can be said that the bus has no time guarantee that guarantees that a predetermined amount of data is transferred within a predetermined time.

[0008]

However, in the prior art described above, in a bus such as a PCI bus, transfer is permitted by a fixed priority method or a round robin method, so that the number of permitted times for each device is fixed. Although they are averaged in proportion and are not out of order, the time to occupy the bus is determined by the device,
If the time for which a certain device occupies the bus becomes longer, the transfer time for another device becomes shorter, and there is a problem that a necessary transfer rate cannot be secured.

For this reason, a device that transfers continuous video stream data cannot transfer data of a frame required for one second (30 frames in the case of NTSC image data). The video is interrupted, and QOS (Quality Of Service, service quality) is not guaranteed.

As described above, in the conventional method, it is difficult to handle time-limited continuous data such as video data, which has been increasing in recent years, while guaranteeing time. In particular, devices having different transfer rates are mixed. If you are remarkable.

When such data is handled on a conventional bus, only a rough time guarantee can be made by software.

SUMMARY OF THE INVENTION In view of the above problems, the present invention provides a bus such as a PCI bus for which QOS is not guaranteed, which guarantees QOS in consideration of device characteristics without changing bus specifications or device-side specifications. It is an object to provide an arbitration device.

[0013]

In order to solve this problem, a bus arbitration apparatus according to the present invention comprises a transfer data counter which is connected to a plurality of devices and measures the amount of data actually transferred for each device. A reference counter that operates on a clock determined from the transfer rate of the device;
Allocation determining means for inputting the value of the transfer data counter and the value of the reference counter and comparing the two values, and for granting a bus permission to the device based on inputs from a plurality of the comparing means The allocation determining means, wherein, at the input from the comparing means, a device in which the value of the transfer data counter is smaller than the value of the reference counter, and the value of the transfer data counter is smaller than the value of the reference counter. When there is a big device,
A bus use permission is given to a device in which the value of the transfer amount counter is smaller than the value of the reference counter.

[0014]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows the configuration of a bus arbitration apparatus according to Embodiment 1 of the present invention, in which n devices are connected.
Bus 2, devices 3-1 to 3-n, transfer request signals (REQ1 to REQn) 4-1 to 4-n from devices, transfer permission signals (GNT1 to GNTn) 5-1 to devices
5-n, allocation determining means 10, reference counter (SC1) 11-1 for device 3-1, transfer data counter (DC1) 12-1, comparing means 13-1, device 3-
2, a reference counter (SC2) 11-2, a transfer data counter (DC2) 12-2, a comparing unit 13-2, and a reference counter (SCn) 11- for the device 3-n.
n, a transfer data counter (DCn) 12-n, and comparison means 13-n.

The bus 2 is a PCI bus standardized for personal computers, and is a 32-bit bus to which a plurality of devices can be connected. This bus is a specification that does not guarantee the time of the bus alone.

The assignment deciding means 10 of the bus arbitrating device 1 decides to which device a bus use assignment is to be made for the requested device from the device transfer request signals 4-1 to 4-n. Then, any one of the transfer permission signals 5-1 to 5-n is returned to the device determined according to the priority order, and the bus use permission is given.

The reference counters 11-1 to 11-n prepared for each device are to count with a clock determined by the transfer rate of the device. The value of the clock can be obtained by dividing the value of the transfer rate required by the device by the bus width and reciprocal.

When the device is registered, the value of this clock is registered in the reference counters 11-1 to 11-n, so that the reference counter starts counting with this value and continues counting.

Transfer data counters 12-1 to 12-n prepared for each device are based on data transferred while each device receives a transfer permission signal, occupies the bus, and transfers data. Count
Measure the amount of data actually transferred.

Comparing means 13-1 to 13-n prepared for each device receive reference signals 11-1 to 11-1 when performing bus arbitration upon receiving a transfer request signal from the device.
1-n is compared with the transfer data counters 12-1 to 12-n, and whether the actual transfer is delayed or advanced is output to the allocation determining means 10.

Next, the operation will be described. FIG. 2 is an explanatory diagram of the operation of the bus arbitration device 1 according to the first embodiment of the present invention. The device 3-1 has a required transfer rate of 32 Mbit / s, and the required transfer rate is 16 Mbit / s. The transfer request signal 4-
FIG. 4 is a diagram illustrating an operation when bus arbitration is performed in response to time lapse after receiving 1, 4-2.

In this case, the device 3-1 is operated at time t0.
It is assumed that the transfer request signal 4-1 has been issued before, and the device 3-2 has issued the transfer request signal 4-2 after time t0 and before t1.

The upper part of FIG. 2 shows how the reference counter (SC1) 11-1 for the device 3-1 and the counter of the transfer data counter (DC1) 12-1 are. 2 is a reference counter (SC) for the device 3-2.
2) 11-2 and transfer data counter (DC2) 12-
2 shows the state of the counter.

Since the transfer rate of the device 3-1 is 32 Mbits / sec, this value is divided by 32 bits, which is the bus width of the PCI bus, and the reciprocal thereof is calculated to obtain the reference counter (SC1) 11-1. A clock is required, which is 1 microsecond. Accordingly, T1 in the upper part of FIG. 2 is 1 microsecond, and the reference counter (SC1) 11-1 continues counting at this interval.

Similarly, the transfer rate of the device 3-2 is 16
Since it is M bits / sec, T2 in the upper part of FIG. 2 is 2 microseconds, and the reference counter (SC2) 11-2 continues counting at this interval.

The operation will be described below based on the passage of time. First, in the bus arbitration at the time t0, the device 3
-2 has not issued the transfer request signal 4-2, and the device 3
Since only the transfer request signal 4-1 from -1 is assigned, the assignment determining means 10 performs assignment to the device 3-1 and outputs a transfer permission signal 5-1. This causes the device 3-1 to start the transfer. At this time, the transfer data counter (DC1) 12-
1 measures the actual data transfer time, starts counting, and counts 1, 2, and 3;
At time t1, DC1 = 8.

Here, in DC1 of FIG. 2, the interval of 3 is long and the interval of 4 is short because the time from the transfer of 3 to the transfer of 4 is long, and the transfer of 4 is performed. This indicates that the time from when the transfer of 5 is performed is short. This is because the device side determines the actual data transfer timing and one data length. This is a specification of the PCI bus.

Next, in the bus arbitration at the time t1, both the device 3-1 and the device 3-2 transmit the transfer request signal 4
-1, 4-2, the assignment determining means 10
It is necessary to decide which one is to be granted bus use.

First, as for the device 3-1, since the value of the reference counter (SC1) 11-1 is 5 and the value of the transfer data counter (DC1) 12-1 is 8, these values are sent to the comparing means 12-1. Since the input is DC1> SC1, the fact that the actual data transfer is ahead of the reference value is notified to the allocation determining means 10. Similarly,
For the device 3-2, the comparing unit 13-2 outputs the DC
It informs the assignment determining means 10 that 2 <SC2 and the actual transfer is later than the reference value.

The assignment deciding means 10 determines from the information of the comparing means 13-1 and 13-2,
2 is given a priority, and a transfer permission signal 5-2 is issued to the device 3-2.

As a result, the device 3-2 performs data transfer using the bus, and the transfer data counter (DC2) 12-2 of the device 3-2 measures the actual data transfer time. Count 2 and 3.

Next, in the bus arbitration at the time t2, similarly to the time t1, it is necessary to give a transfer permission to either the device 3-1 or the device 3-2. Comparing means 13-1 and 13-2 compare the value of the transfer data counter with the value of the reference counter and output the result to the allocation determining means 10. At time t2, the device 3-1
Is behind the reference because of DC1 <SC1, and the device 3-
No. 2 outputs to the assignment determining means 10 that DC2> SC2 and leads the reference. Therefore, the allocation determining means 10
In order to give priority to a device that is behind the reference, a transfer permission signal 5-1 is issued to the device 3-1 and the device 3
-1 performs data transfer using the bus.

The same applies hereafter, and the assignment determining means 10 detects the device which is further behind the reference by the input from the comparing means 13-1 and 13-2 for comparing the value of the transfer data counter with the value of the reference counter. , A transfer permission signal is given to permit the use of the bus.

By repeating this, bus arbitration can be advanced so as to satisfy the transfer rate required for each device.

As described above, even in a bus such as a PCI bus, which does not have a guaranteed time, a time can be assured in consideration of device characteristics only by a bus arbiter without changing the bus specifications and device specifications. . As a result, continuous data such as multimedia data, which has been increasing in recent years,
Especially when a plurality of video data are processed on a personal computer, the QOS can be guaranteed.

In particular, even when devices that input and output video data having greatly different transfer rates are mixed, QOS can be guaranteed for each device, and the effect is remarkable.

Further, since the time guarantee is realized only by the bus arbitration device, the bus management processing for time guarantee, which is performed by the conventional control software, becomes unnecessary. Development can be greatly reduced.

In the first embodiment of the present invention, the reference counters 11-1 to 11-n use the devices 3-1 to 3-
Find the value of the clock determined by the transfer rate of n
Although this value was used as it is, this value is the maximum value of the reference value. In practice, a value slightly smaller than this value is used as the clock of the reference counter, so that the transfer can be performed earlier and time can be given. By doing so, the effect can be enhanced.

In the first embodiment of the present invention, the number of devices simultaneously requesting transfer is two. However, even if the number of devices becomes three or more, the allocation determining means 10 causes the most delay with respect to the reference value. The arbitration can be similarly performed by giving a priority to the device in question, and the effect described above does not change.

In the first embodiment of the present invention, it has been described that all connected devices need to guarantee QOS. However, there is no continuity among devices,
There is also a case where the OS does not need to be guaranteed. Even in this case, it is possible to solve the problem by making the clock value of the reference counter sufficiently larger than that of a device requiring another QOS. Therefore, even when various devices are mixed, the above-described effect does not change.

[0042]

As described above, according to the present invention, the PCI
Even on a bus such as a bus that does not have a guaranteed time, it is possible to guarantee the time in consideration of the characteristics of the device only by the bus arbitration device without changing the bus specifications and device specifications.
As a result, it is possible to guarantee QOS even when a plurality of continuous data such as multimedia data, which have been increasing in recent years, particularly video data, are processed on a personal computer.

In particular, even when devices that input and output video data having greatly different transfer rates coexist, QOS can be guaranteed for each device, and the effect is remarkable.

Further, since the time guarantee is realized only by the bus arbitration device, the bus management processing for the time guarantee, which is performed by the conventional control software, becomes unnecessary. Development can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a bus arbitration device according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an operation of the bus arbitration device according to the first embodiment of the present invention.

FIG. 3 is a functional explanatory diagram of a general bus arbitration device.

[Description of Signs] 1 bus arbitration device 2 bus 3-1-3-n device 1-n 4-1-4-n transfer request signal (REQ) from device 1-n 5-1-5-n device 1 Transfer permission signal (GNT) for the device 1 to n 10 Assignment determining means 11-1 to 11-n Reference counter (SC) for the device 1 to n 12-1 to 12-n Transfer data counter (DC) for the device 1 to n 13- 1 to 13-n Comparison means for devices 1 to n 100 Bus arbitration device 101 Transfer request signal (REQ) 102 Transfer permission signal (GNT)

Claims (1)

[Claims] 1. A transfer data counter which is connected to a bus together with a plurality of devices and measures the amount of data actually transferred for each device, a reference counter which operates with a clock determined from a transfer rate of the device, and Having a comparing means for inputting the value of the transfer data counter and the value of the reference counter and comparing two values, and determining an assignment for granting a bus use permission to the device based on inputs from a plurality of the comparing means Means for determining whether the value of the transfer data counter is smaller than the value of the reference counter, and the value of the transfer data counter is smaller than the value of the reference counter. When there is a device with a larger value, the value of the transfer amount counter is smaller than the value of the reference counter. Bus arbitration device, characterized in that it gives the bus use permission to.