JP2507807B2 - Distributed arbitration method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] A bus control method for a general-purpose system bus is intended to reduce the delay time associated with an increase in the number of connection units and to relax the limit on the number of units that can be connected to the bus. A plurality of units connected to the system bus, a bus handler that is connected to the system bus and manages the right to use the bus, and a bus handler,
When the bus usage right request signal is input from a plurality of units under its control, this is output to the bus handler as one bus usage right request signal, and when the bus usage grant signal is given from the bus handler. A plurality of bus arbiters that give the right to use the bus in order from the highest priority to the plurality of units under their control are provided, and each bus arbiter is configured to be connected to the plurality of units through the system bus. The bus handler is configured so that the bus arbiter can be treated as a unit for handling the bus usage right.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control system in a general-purpose system bus, and more specifically, a centralized arbitration system in which a bus management right management unit is provided in an information transfer bus used in an information processing apparatus. The bus usage right is configured so that the bus usage right request signal and the bus usage permission signal can be exchanged between the unit connected to the bus and the unit managing the bus to monopolize the bus. The present invention relates to a bus control method in a system.

[Prior Art] FIG. 4 is a block diagram showing an embodiment of a conventional bus system. In a general-purpose bus system in a computer system, a plurality of units 2 connected to a system bus 1 (hereinafter, simply referred to as a bus) need to obtain a bus use right when transferring data using the bus 1. is there. In order to obtain the right to use the bus, the unit 2 concerned manages the right to use the bus.
To the bus request BQR which is a bus usage right request signal
To issue. A bus grant signal BGR, which is a bus use permission signal, is issued to the bus handler 3 that has received the signal BQR and the unit 2 that has issued the signal. Only when the unit receives this BGR signal, the use of the bus is permitted and the bus can be used.

FIG. 5 is a block diagram of the bus handler in FIG. The bus handler 3 has a built-in arbitration circuit 3a for adjusting the bus, inputs bus usage right request signals BRQ-1 to BRQ-6 from a plurality of units 2, and sequentially inputs the units with the highest priority. Bus enable signal BG
It is designed to give R-1 to BGR-6. When receiving the data transfer end signal BCPT from the unit 2, the arbitration circuit 3a outputs the bus use permission signal BGR to give the right to use the bus to the next unit 2.

[Problems to be Solved by the Invention] In a computer system including a plurality of units 2, BRQ signals may be issued from a plurality of units 2 at the same time. BGR signal is given to the unit 2 having a higher priority. Therefore,
The bus handler 3 receives a bus use right request signal issued from all units 2 connected to the bus 1, and the bus handler 3 outputs a signal permitting use of the bus 1 to all units 2. Has been done.

In the conventional example, in order to greatly expand the system scale, it is necessary to connect the unit 2 to the bus 1 and connect the bus 1 usage right request signal and the bus usage permission signal to the bus handler 3. In the conventional example shown in FIGS. 4 and 5, 13 signal lines are used to manage the right to use the bus to which 6 units are connected, but the system configuration becomes large. As the number of units connected to the bus 1 increases, the number of signal lines required for managing the usage right of the bus 1 increases.

However, there is a limit to the number of units that can be connected to the bus 1 due to the limit of the number of pins such as the connector that connects the bus 1, and therefore there is a problem that the system scale cannot be increased beyond a certain level.

Further, when the number of units increases, the bus arbitration circuit (arbitration circuit 3a) in the bus handler 3 becomes large, and the amount of hardware increases. Moreover, there is a problem that the delay time of the signal also increases due to the increase in the size of the circuit.

In view of such a point, the present invention divides the bus into several groups, and connects the units (bus arbiters) that manage the bus usage right in each group of buses to divide the arbitration circuit and delay. It is an object of the present invention to provide a distributed arbitration method which can reduce the time and further reduce the number of units that can be connected to the bus by managing the bus arbiters by the bus handler.

[Means for Solving the Problems] FIG. 1 is a block diagram showing the principle of the present invention. The same parts as those in FIG. 4 are designated by the same reference numerals. In the figure, the system bus 1, a plurality of units 2 connected to the bus 1, and a bus handler 3 for controlling the bus use right of these units 2 are the same as those in FIG. 10 is connected to the bus handler 3, and when a bus usage right request signal is input from a plurality of units under its control, this is output to the bus handler 3 as one bus usage right request signal, and at the same time, the bus handler 3 When a bus use permission signal is given from 3, the bus arbiter gives a bus use right to a plurality of units under its control in descending order of priority.

A plurality of these bus arbiters 10 are provided, and the system bus 11 is connected to each bus arbiter 10.
A plurality of units 12 are connected to the.

[Operation] In such a configuration, by connecting the bus arbiter 10 to the bus handler 3, the bus can be divided into a plurality of groups for use, and the system configuration can be expanded. Each bus arbiter 10 is a subordinate unit 12
Bus usage right request signal BRQ is arbitrated and the highest priority B
Only the RQ signal is extracted and given to the bus handler 3. When the bus handler 3 receives the bus use right request signal from the unit 2 or the bus arbiter 10 under its control, the bus handler 3 gives a bus use permission signal to the unit 2 or the bus arbiter 10 having the highest priority.

The bus handler 3 does not see the unit 12 under the bus arbiter 10, but sees all the units 12 under the bus arbiter 10 as one unit. Therefore, it seems to the bus handler 3 that the number of units 12 connected under the bus arbiter 10 is increased by the number of the bus arbiters 10.

With such a configuration, it is possible to prevent an increase in signal time delay due to the increase in the number of units, and even if the number of units increases, the number of signal lines does not increase as much as in the conventional example, so that the system can be easily expanded. can do.

[Embodiment] FIG. 2 is a block diagram showing an embodiment of a bus arbiter according to the distributed arbitration system of the present invention. In the figure, BUF1 to BUF15 are buffers inserted in the respective signal lines, 21 is an arbitration circuit, and 22 is an OR circuit.

To the arbitration circuit 21, the bus use right request signals BRQ-1 to BRQ-6 from the subordinate units, the bus use permission signal BGR-E from the bus handler, and the data transfer end signal BCRT from the unit are input. Also, a bus use permission signal can be output to each unit.

The OR circuit 22 takes the OR of the six bus use right request signals and outputs it as one bus use right request signal BRQ-E to the bus handler.

When the bus use permission signal BGR-E is input from the bus handler, the arbitration circuit 21 sends the bus use right request issued from the subordinate unit to the highest priority one (priority is predetermined for each unit). Because
Based on this, the highest priority unit that issued the bus usage right request can be known.) Bus usage permission signals (BGR-1 to BGR
Any one of -6) is given. After that, when the data transfer end signal BCPT is returned from the unit (in this case, the processing of the unit is the data transfer processing),
A bus use permission signal is given to the remaining units which have issued the bus use right request signal, and similarly, the unit waits for the arrival of the data transfer end signal. When the bus use right request signal disappears, the bus use right request signal from the OR circuit 2 disappears. This allows the bus handler to know that there are no more requests.

FIG. 3 is a block diagram showing an embodiment of the bus handler. In the figure, BUF11 to BUF27 are buffers inserted in the respective signal lines, and 31 is an arbitration circuit. The arbitration circuit 31 receives the bus use right request signals BRQ-1 to BRQ-6 from the six subordinate units and the bus use right request signals BRQ-E1 and BRQ-E2 from the bus arbiter, and inputs them to the subordinate units. For the bus use permission signal BGR
-1 to BGR-6, and two bus use permission signals BGR-E1 and BGR-E2 can be output to the bus arbiter. Further, the data transfer end signal BCPT from each unit under control and each bus arbiter which has been ORed beforehand (the circuit for ORing is not shown) is inputted.

When the bus use right request signal from the subordinate unit and the bus arbiter is input, the arbitration circuit 31 sends out a bus use permission signal to a higher priority one.
One of BGR-1 to BGR-6 for the subordinate unit, and BGR-E for the bus arbiter.
Outputs either 1 or BGR-E2 signal. After that, when the data transfer end signal BCPT is returned, a bus use permission signal is issued to the remaining bus use right request signal, if any.

Although the bus arbiter and the bus handler require management, it is of course possible to transfer data between arbitrary units.

[Effects of the Invention] As described above, according to the present invention, the amount of hardware of a unit (bus handler or bus arbiter) that manages one bus can be reduced by dividing the bus, and the amount of hardware can be increased. It is possible to prevent an increase in time delay caused by Further, it is easy to make the system configuration large-scale, and moreover, the system can be expanded in a wide range by regarding the expanded bus arbiter and the unit under the bus arbiter as one case.

[Brief description of drawings]

1 is a block diagram showing the principle of the present invention, FIG. 2 is a block diagram showing an embodiment of a bus arbiter according to the distributed arbitration system of the present invention, and FIG. 3 is an implementation of a bus handler according to the distributed arbitration system of the present invention. FIG. 4 is a block diagram showing an example, FIG. 4 is a block diagram showing an example of a conventional bus system, and FIG. 5 is a block diagram of the bus handler in FIG. In FIG. 1, 1 and 11 are system buses, 2 and 12 are units, 3 is a bus handler, and 10 is a bus handler.

Claims (1)

(57) [Claims] 1. A centralized arbitration system in which a unit for managing the right to use a bus is provided in a bus for information transfer used in an information processing device, and the right to use the bus manages a unit connected to the bus and the bus. A system bus (1) and a system bus (1) connected to the system bus (1) configured to enable the exclusive use of the bus by transmitting and receiving a bus use right request signal and a bus use permission signal between the units. A plurality of units (2), a bus handler (3) that is connected to the system bus (1) and manages the right to use the bus, and a plurality of units that are connected to the bus handler (3) and are under its control. When a bus usage right request signal is input from the unit, this is output to the bus handler (3) as a single bus usage right request signal, and the bus usage right is requested from the bus handler (3). When a use permission signal is given, a plurality of bus arbiters (10) that give the right to use the bus to the plurality of units under their control are provided in order from the one with the highest priority. It is configured to be connected to a plurality of units (12) via 11), and the bus handler (3) is configured so that the bus arbiter (10) can be treated as a unit for controlling the bus usage right. Characterized distributed arbitration method.