JPH0895906A - Bus arbitrating device - Google Patents

Abstract

PURPOSE: To prevent a bus from being occupied by any specified bus master without lowering efficiency at the time of bus arbitration and to enable a user to perform the bus arbitration while considering the degree of importance for respective bus masters by providing a weighting setting part for setting the weighting of respective bus requests from the bus masters on the input side of a round-robin bus arbitrating circuit. CONSTITUTION: On the input side of a round-robin bus arbitrating circuit 11, a weighting setting part 15 for bus request outputs is provided to set the weighting of bus request outputs corresponding to the respective bus masters by respectively dividing request outputs BR1-BR3 of the bus from the bus masters into a prescribed number of outputs in advance. When the bus requests are outputted from the respective bus masters, the bus request output signals BR1-BR3 are divided into a prescribed number by the weighting setting part 15 and inputted to the round robin bus arbitrating circuit 11. Then, permitting signals BG1-BG3 are outputted to the bus masters, which permits the use of the bus, based on the output of the round-robin bus arbitrating circuit 11.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbitration device which adjusts information transfer requests of devices using a bus in a computer system.

[0002]

In the system bus of a computer system, in addition to the main master CPU, the slave C
A plurality of bus masters such as PU and DMA controllers are connected, and a bus request for requesting the use of the bus for information transfer is output from these devices. The bus arbitration device determines the priority of the bus use of each bus master based on the bus request output from each bus master. For this bus arbitration device, priority is given to early bus requests, and when the time is the same, a non-procedural bus arbitration device that adjusts in a non-procedure and the actual use of the previous bus are considered to adjust the current bus use. There is a round robin bus arbitration device.

This non-procedural bus arbitration device has a bus request mask circuit and a priority order determination circuit, and these two circuits form the basic part of the bus arbitration device. Further, the round robin bus arbitration device has a priority order determination circuit and a latch circuit for storing the bus master that has acquired the bus immediately before, and these two circuits form the basic part of the bus arbitration device.

Next, the operations of the non-procedural bus arbitration device and the round robin bus arbitration device thus configured will be described.

First, the arbitration operation of the non-procedural bus arbitration device will be described. In the non-procedural bus arbitration device, when there is a bus request to the bus request mask circuit, the bus request mask circuit is masked so that no more bus requests are accepted, but the bus request occurs completely asynchronously. Therefore, it is possible that requests for multiple buses are captured at the same timing. In such a case, the priority of each bus request is determined by the priority determining circuit, and the bus arbitration is performed according to the determined priority.

Next, in the round robin bus arbitration device,
In the case of a timing in which requests for multiple buses are simultaneously captured, the priority determination circuit ensures that the bus master that previously acquired the bus has the lowest priority according to the signal from the latch circuit that stores the bus master that used the previous bus. The priority of the bus request is determined, the bus arbitration is performed according to the determined priority, and as long as the determined bus request exists, the other bus requests are masked.

[0007]

However, in the non-procedural bus arbitration device, which is one of the conventional bus arbitration devices, if there is a bus request to the bus request mask circuit, the requests of other buses are not accepted. Since the bus request mask circuit is masked like this, the system main CPU
The main CPU releases the bus,
There is a problem that the bus requesting device has to take the procedure of acquiring the bus one by one, and if another bus request occurs while a bus master is acquiring the bus, the efficiency of the bus arbitration decreases.

Further, in the other round robin bus arbitration device of the conventional bus arbitration device, since the priority of the bus is determined only by the type of the bus master which has used the bus immediately before, the data transfer rate of each bus master. However, there is a problem that the priority cannot be determined in consideration of the importance of the bus master related to the access frequency to the memory on the bus and the amount of memory buffer.

The present invention solves such a conventional problem, prevents bus monopolization by a specific bus master, and considers the importance of each bus master without lowering the efficiency during bus arbitration. It is an object of the present invention to provide a bus arbitration device capable of performing bus arbitration.

[0010]

Therefore, in the present invention, in a bus arbitration device that includes a round robin bus arbitration circuit and arbitrates bus requests from a plurality of bus masters connected to a bus, each bus request from the bus master. A weighting setting unit for setting the weighting is provided on the input side of the round robin bus arbitration circuit.

The weight setting unit divides the bus request output from the bus master according to the weight of the bus master and inputs it to the round robin bus arbitration circuit.

Further, the number of divisions of the bus request output can be changed by a control signal.

[0013]

In this arbitration device, since the round robin bus arbitration circuit is used, the bus arbitration can be efficiently performed.

Further, the bus request output from the bus master having a high degree of importance is divided into a large number and is input from many input terminals of the round robin bus arbitration circuit, and therefore is selected in the arbitration of the round robin bus arbitration circuit. The probability increases.

Further, the number of bus request outputs from each bus master can be increased or decreased by a control signal.

[0016]

FIG. 1 shows the configuration of a bus arbitration device according to an embodiment of the present invention. In FIG. 1, the bus arbitration device has a plurality of input terminals BA1 to BA6 and a plurality of output terminals BY1 to B.
A round robin bus arbitration circuit 11 having Y6 and a plurality of control input terminals Q1 to Q6, and a plurality of input terminals D1 to D6 and a round robin connected to each of a plurality of output terminals BY1 to BY6 of the round robin bus arbitration circuit. A latch circuit 12 having a plurality of output terminals Q1 to Q6 and a trigger input terminal BTRG connected to each of a plurality of control input terminals Q1 to Q6 of the bus arbitration circuit, and a plurality of output terminals BY1 of the round robin bus arbitration circuit 11. To BY6, a bus request output circuit 13 having a plurality of input terminals connected to each of them, and an output terminal for outputting a bus request signal BR-OUT to the main CPU of the system; and the round robin bus arbitration circuit. It has a plurality of input terminals connected to each of a plurality of 11 output terminals BY1 to BY6 and outputs a bus enable signal BG1 to BG3 to each bus master (not shown). Allow output circuit
14 and a bus request output weight setting unit 15 that sets the weight of the bus request output according to the bus master by dividing each of the bus request outputs BR1 to BR3 from each bus master into a predetermined number of outputs in advance (here, BR1, BR2, and BR3 are divided into three, two, and one, respectively, and are connected to (input BA1, BA3, BA5), (input BA2, BA4), and input BA6 of the round robin bus arbitration circuit 11. , And the weighting between each bus master is set to 3: 2: 1).

In this bus arbitration device, when a bus request is output from each bus master, the bus request output signals BR1 to B
R3 is divided into a predetermined number in the weight setting unit 15 and applied to the input terminals BA1 to BA6 of the round robin bus arbitration circuit 11, which is a latch that stores the previous bus master used. Output signal from circuit 12
Latch output signals Q1 to Q6 as controlled by Q1 to Q6
In response to this, the round robin bus arbitration circuit 11 outputs one of the output signals BY1 to BY6 according to the priority order shown in FIG. 3 described later.

This signal is latched by the latch circuit 12 and is used by the round robin bus arbitration circuit 11 as a control signal for determining the priority of the next bus request output. It is supplied to the output circuit 13, the bus use request signal BR-OUT is output to the main CPU of the system, and further supplied to the bus permission output circuit 14 composed of a plurality of OR circuits to permit the use of the bus. Enable signals BG1 to BG3 are output to the bus master.

Next, the main CPU of the system which has received the request for using the bus releases the bus, and the bus master which has been granted the bus use transfers the data using the bus.

Next, in FIG. 2, for simplification of explanation, the output signal of the round robin bus arbitration circuit 11 (BY1
~ BY6) shows a logic circuit for forming one output signal (BY1). This logic circuit has signal BA1, signal B
Inverted signal BA2 'of A2, inverted signal BA3' of signal BA3, signal BA4
6 of the inverted signal BA4 ′ of the signal BA5 ′, the inverted signal BA5 ′ of the signal BA5, the inverted signal BA6 ′ of the signal BA6, and the output signal Q1 of the latch circuit 14.
A first AND circuit 21 having one input, a second AND circuit 22 having five inputs of the signal BA1 and the inverted signal signals BA3 'to BA6' and one input of the output signal Q2 of the latch circuit 14, and a signal
A third AND circuit 23 having four inputs of BA1 and inverted signals BA4 to BA6 and one input of the output signal Q3 of the latch circuit 14, and a signal
A fourth AND circuit 24 having three inputs of BA1 and inverted signals BA5 and BA6 and one input of the output signal Q4 of the latch circuit 14, two inputs of the signal BA1 and the inverted signal BA6, and an output signal of the latch circuit 14.
A fifth AND circuit 25 having one input of Q5, a sixth AND circuit 25 having one input of the signal BA1 and one input of the output signal Q5 of the latch circuit 14, and first to sixth AND circuits 21 to 21- It is composed of an OR circuit 27 which supplies an output signal of 26.

In this logic circuit, when BA1 is input, Q
The states that BY1 can output vary depending on the signals from 1 to Q6. That is, if Q6 is “1”, BY1 can be output without fail. When Q5 is “1”, BY1 can be output unless BA6 is “1”. When Q4 is “1”, BY1 can be output unless BA6 and BA5 are “1”. Also, when Q1 is "1", BY1 cannot be output unless all of BA2 to BA6 are "0". In this way, in this logic circuit, the priority order of BA1 changes according to the signals of Q1 to Q6.

The logic circuit for forming the other output signals (BY2 to BY6) is the same as the logic circuit shown in FIG.

The round robin bus arbitration circuit 11 has a circuit configuration similar to that shown in FIG. 2 so that when the control signal Q1 is input (that is, the previous round BY1 is output from the round robin bus arbitration circuit 11, the latch circuit this time is used. When the control signal Q1 is output from 12), output BY1 to BY6
Set the priority order of ＞ BY3 ＞ BY4 ＞ BY5 ＞ BY6 ＞ BY1. For example, when BA3 and BA4 are input at the same timing,
Output BY3, which has the highest priority. FIG. 3 shows the relationship of priorities set by the round robin bus arbitration circuit 11 in accordance with the previous output.

Next, the operation when a plurality of bus requests are output to the bus arbitration circuit at the same timing will be described.

It is now assumed that the immediately preceding bus request output is BY3. In this state, when the bus request outputs BR1 and BR2 are output from the bus master 1 and the bus master 2, respectively, the bus request outputs BA1 to BA5 divided by the weight setting unit 15
One bus request is input to the round robin bus arbitration circuit 11, but since it is assumed that the immediately preceding bus request output is BY3 as described above, the latch circuit 12 latches the signal BY3. Therefore, since a signal is input to the control input Q3 of the round robin bus arbitration circuit, the round robin bus arbitration circuit 11 is changed from the priority order shown in FIG.
BY4 has the highest priority, and the logic circuit for forming the bus request output signal shown in FIG.
Print only 4. Therefore, since the bus request output signal BY4 is output when the bus request output BR2 from the bus master 2 is output as shown in FIG. 1, the bus request from the bus master 2 is given the highest priority. By dividing the bus request output from each bus master in this way, for example, the bus request output BR1 from the bus master 1 is divided into three, so that the bus request output BR3 from the bus master 3 is not divided. The bus acquisition right can be obtained about three times as much as the output. Therefore, it becomes possible to weight the bus requests according to the performance and importance of the bus master.

Further, in FIG. 1, the weight setting section 15 sets the weight by fixedly wiring, but FIG.
As shown in FIG. 5, the weight setting unit 15 may be composed of a plurality of logics including first to sixth AND circuits 151 to 156. That is, the first AND circuit 151 inputs the bus request signal BR1 and the control signal Set1 and outputs the signal BA2, and the second AND circuit 152 outputs the bus request signal BR1 and the control signal Se.
t2 is input, signal BA3 is output, and the third AND circuit 153
Inputs the bus request signal BR2 and control signal Set3, and sends the signal B
A5 is output, and the fourth AND circuit 154 outputs the bus request signal B
The R2 and the control signal Set4 are input, the signal BA6 is output, the fifth AND circuit 155 inputs the bus request signal BR3 and the control signal Set5, outputs the signal BA8, and the sixth AND circuit 156 is The bus request signal BR3 and the control signal Set6 are input and the signal BA9 is output.

Weighting can be variably set depending on whether or not each of the control signals Set1 to Set6 is applied to each of the first to sixth AND circuits 151 to 156. By doing this, the weights of the three bus masters can be arbitrarily set according to the system, such as equivalent 1: 1: 1 or 3: 1: 1 with only one protruding, or 3: 2: 1. can do.

As described above, the bus arbitration device of the present invention can perform weighted bus arbitration in consideration of the importance of the bus master.

Further, in this device, when a bus request is made by another bus master while one bus master is acquiring the bus, the round robin bus arbitration circuit continuously outputs the bus request. When a bus master that has made a request later acquires the bus, the procedure of requesting the bus to the main CPU of the system and releasing the bus of the main CPU can be omitted.

[0030]

As is apparent from the above description of the embodiments, in the bus arbitration device of the present invention, the bus master with the higher priority continues to occupy the bus, and the bus master with the lower priority cannot obtain the bus use right. While avoiding such a situation, it is possible to perform bus arbitration so that a bus master having a high degree of importance and ability has a large number of opportunities to acquire the bus. Further, by calculating the capacity of each bus master and increasing / decreasing the number of required bus outputs according to the calculation, it is possible to set the optimum weighting corresponding to the capacity difference of each bus master.

Further, the configuration in which the number of required bus outputs is adjusted by the control signal makes it possible to support a plurality of systems.

Since the bus arbitration device of the present invention uses the round robin bus arbitration circuit, when one bus master acquires the bus, another bus master requests the bus, The bus opening procedure can be omitted, and efficient bus arbitration can be performed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a bus arbitration device according to an embodiment of the present invention,

FIG. 2 is a diagram showing a part of a round robin bus arbitration circuit in the bus arbitration device of the embodiment;

FIG. 3 is a diagram showing priorities set by the round robin bus arbitration circuit;

FIG. 4 is a block diagram showing a configuration of a bus arbitration device according to another embodiment of the present invention.

[Explanation of symbols]

 11 Round robin bus arbitration circuit 12 Latch circuit 13 Bus request output circuit 14 Bus permission output circuit 15 Weight setting section 21 to 26 AND circuit 27 OR circuit 151 to 156 AND circuit

Claims (3)

[Claims] 1. A round robin bus arbitration circuit is provided,
In a bus arbitration device that arbitrates bus requests from a plurality of bus masters connected to a bus, a weight setting unit that sets the weight of each bus request from the bus master is provided on the input side of the round robin bus arbitration circuit. And a bus arbitration device. 2. The bus according to claim 1, wherein the weight setting unit divides a bus request output from the bus master according to a weight of the bus master and inputs the divided bus request output to the round robin bus arbitration circuit. Arbitration device. 3. The bus arbitration device according to claim 2, wherein the number of divisions of the bus request output is made variable by a control signal.