JPH0496165A - System bus arbitrator - Google Patents

Abstract

PURPOSE:To reduce arbitration time by deciding the candidate of the next device to use a system bus in the inside of a block by comprising arbitration for a right of using system bus between a block inside and a block in a system of two stages. CONSTITUTION:A system bus arbitration part 2 is provided which divides the system bus 1 into the blocks 9-11 comprised of shared plural devices, and decides by which blocks 9-11 in the system the system bus 1 is used, and issues permission. Also, in-block arbitration parts 18, 19, and 20 are provided which decide by which blocks 9-11 in the system the system bus 1 is used. Therefore, this arbitrator can be applied when the number of devices using the system bus 1 is increased, or to a multi-CPU system, etc., and also, the work of the system bus arbitration part 2 can be performed in parallel with that of the in-block arbitration parts 18-20, respectively. Thereby, the arbitration time can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a system bus arbitration device for a computer equipped with a CPU, memory, peripheral devices, and the like.

2. Description of the Related Art In recent years, the performance of microprocessors has been improved in a short period of time by pattern design using submicron rules within semiconductor chips and by implementing internal pipeline processing. In order to improve the overall performance of a system using such a high-performance microprocessor, there are methods to shorten the execution cycle time and to construct a plurality of microprocessors in the system. In systems with many devices that require the use of such a system bus,
It is necessary to efficiently arbitrate the right to use the system bus, and it is also necessary to be able to cope with future system expandability. Hereinafter, each conventional devine arbitration for a request for the right to use a system bus will be explained with reference to FIGS. 3 and 4.

As shown in FIG. 3, a system bus arbitration unit 2 is provided inside the system, and a system bus 1 use request signal 12-1.13-1 is sent from a device that can request the right to use the system bus 1. .

14-1.15-1.16-1.17-1, and determines the execution cycle of the currently used device according to the priority of the current system bus 1 usage de- pin and the system bus 1 requesting device. After confirming that it has finished, allow the next device to use system bus 1.

Each of the signals described above is shown in FIG. 4 and will be explained.

Here, as shown in Figure 3, the system requires the use of system bus 1 by CPU
1 (4), CPU2 (5), CPU3 (6)
)CPU, DMA(s) and Ethernet
(7). Further, the system bus arbitration unit 2 sends a use permission signal to notify permission to use the system bus 1 at 12-2.
°12-2, 14-2, 16-2, 16-2.

1 finish - 2.

At time t(a) in FIG. 4, three devices request use of system bus 1. In this system, CPU○(3
) > CPU1 (4) > CPU2 (5) > CPU3 (6)
) DMA (8)) Ethernet (7) has the highest priority for the right to use the system bus 1. According to this priority, the system usage requests (RQCPUo, RQCPUl) of the three devices at time t (a).

RQETH-L”), the CPU
0(3) is granted the right to use the system bus (AKC
PUQ=“L”). CPU0 (3) at time t (c)
The execution of t (d) ends (RQCPUo=“H”)
Then, the next device CPU 1 (4) is permitted to use the system bus 1 (AKCPU1="L"). At t (e), CPU 1 (4) finishes execution (
RQCPth=NH”).Here, the next use of system bus 1 is determined, but CPU0 (3) and Ether
Two devices in net(7) are requesting t (
Since Ethernet (7) has not yet used system bus 1 since point a), it does not follow the priority order and uses t (
f), the right to use the system bus 1 is granted to the Ethernet (AKETH = "L"). In this way, the system bus arbitration unit 2 in turn grants the use of the system bus 1 to the device requesting the use of the system bus 1. permission.

Monitor.

Problems to be Solved by the Invention In such a conventional system bus arbitration device, when the system configuration is changed 9 and the number of devices requesting use of the system bus 1 is increased, the system bus arbitration unit 2 is changed. The number of system buses must be changed during system design. In addition, the system bus request signal 12-1 is sent as many times as the number of devices requesting to use the system bus 1.
゜13-1.14-1.15-1.16-1.

1 completion-1 and system bus use permission signal 12-2.

13-2, 14-2, 15-2, 16-2.

17-2 is required on system bus 1, many CP
In a system in which U is mounted on F, there is a problem in that the number of signals forming the system bus 1 increases.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide an excellent system bus arbitration device with a simple configuration.

Means for Solving the Problems In order to achieve the above object, the present invention includes a system bus that transmits address, data, and control signals, a system bus arbitration unit that manages the right to use the system bus,
a block including a plurality of devices that share the system bus; a bus requester section that requests the right to use the system bus of the block; and a bus requester unit that requests the right to use the system bus of the block; It is equipped with an intra-block arbitration section that independently determines the .

Effect The present invention has the above-described configuration, and divides the system bus 1 into blocks each consisting of a plurality of devices that share the system bus 1.
a system hash arbitration unit 2 that determines which block within the system will use the system bus 1 and performs permission; an intra-block arbitration unit 1 B that determines which device within the block will use the system bus 1; 19 and 20, it can be applied to cases where the number of devices using the system bus 1 is increased or to a multi-CPU system configured with a large number of devices.

Also, the system bus arbitration unit 2 and the intra-block arbitration unit 18,
19 and 20 perform their work in parallel, so
The arbitration time can be reduced compared to the conventional case where the system bus arbitration unit 2 arbitrates for all devices requesting the use of the system bus 1.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIGS. 1 and 2.

As shown in the figure, there is a system bus 1 consisting of signals such as addresses, ports, and controls within the system, and a system bus arbitration section 2 that determines the use of the system bus 1.
The first block 9 has CPU O(3) and CPU1G4.
), but the second block 1o has CPU 2 (5) and C
P U 3 (e), but the third block 11 has Ethe
rnet 7 and DMA8 are each implemented. In this embodiment, the system bus arbitration section 2 only needs to arbitrate for three blocks from the first block 9 to the third block 11, and the system bus 1 is sent as a signal from the system bus arbitration section 2. is each system bus request signal 2
1-1゜22-1.23-1 and permission signal 21-2.22
Only 6 pieces of -2°23-2 are required.

The bus requester sections 24-1, 24-2, and 24-3 combine system bus use requests from multiple devices into one, and the system bus arbitration section 2 is given only the request signal for each block. No information is given as to whether the system bus request signal is from a device.

Each signal for the operation of this embodiment is shown in FIG. 2 and will be explained.

At time t (a), CPU0 (3) and CPU1 (4).

Each of the CPU 2 (5) and the DWA 8 issues a request to use the system bus 1. A request to use the system bus 1 as a block is simply output to the system bus arbitration unit 2 if there is a request from a device within the block. In this embodiment, the priorities are in the order of first block 9>second block 10>third block 11, and if multiple devices within the same block request to use the system bus 1, permission is granted. , satisfies the requests of all devices and grants them the right to use system bus 1. This time, request for use of system bus 1 of each block at time t (a) (RQSL1="L", RQSL2="L"R
For QS L3-"L'°), the system arbitration unit 2 grants the right to use the system bus 1 (AKSL1="L") to the first block 9 at time t (b). Also,
In this embodiment, CPUo(3):>CPU1(4).

CPU 2 (5):> CPU 3 (6), DM
A8) Priority is also set for each device inside the block in the order of Ethernet7. At time t (a), CPU 0 (3), CPU 1 (4), CPU
2 (clause, DMA5 each issues a request to use system bus 1, the first block 9. the second block 10. the third
Block 11 receives the system bus use request signal (RQSL
1=“L”, RQSL2”L”, RQSL3-“L Pa)
Therefore, the right to use system bus 1 is given to the first flock at time t(b) (AKSL1="L").
). The intra-flock arbitration unit 18 causes the CPU0 (3) to use the system bus 1 according to the device priority, and
At point (c), execution of CPUo(3) ends (RQCPU
.

“H”), and at time t (d), the CPU
4) Allow use of system bus 1. During this time, RQSL 1 is set to "L" for the system arbitration unit 2 so that the first block 9 can continuously use the system bus 1. At time t(e), execution of CPU1(4) ends (
After confirmation (RQCPU1="H"), the request to use system bus 1 as the first block is canceled in order to hand over the right to use system bus 1 to another block (RQCPU1="H").
1-“H”). At time t (f), the right to use the system bus 1 is given to the second block 10 (AKSL2="L").
”) During this time, the intra-block arbitration unit 1 of the first block 9
9 restarts arbitration of devices within the block separately from the system bus arbitration unit 2, determines the device at the time when the next first block 9 can be used, and confirms that other blocks are finished using system bus 1. After that, issue the system bus use request signal again.

As described above, according to the system bus arbitration device according to the embodiment of the present invention, the bus requester units 24-1 and 24-1 request the right to use the system bus 1 in each block 9, 10.11.
2, 24-3, and the arbitration unit 18 in each pro block block.
, 19, 20, and a system bus arbitration unit 2 that manages usage rights in response to requests for usage rights of the system bus 1 from each block. Since B, 19, and 20 each execute their work in parallel, compared to the conventional case where arbitration is performed for all devices requesting the use of the system bus 1, time is reduced and devices requesting the use of the system bus are It can be adapted even if it increases.

Effects of the Invention As is clear from the above embodiments, the present invention has a two-stage configuration for arbitration of system bus usage rights between blocks within the lever block and within the system. By determining this, even with a two-stage arbitration device, it is possible to reduce the arbitration time, and even if the number of devices inside the block increases, system changes can be made only within the block, making it possible to change the system configuration in the future. This makes it possible to provide a system bus arbitration device that is adaptable and extremely advantageous in practice.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of the present invention, Fig. 2 is a signal diagram showing the transition of operation of this embodiment, Fig. 3 is a block diagram of a system including a conventional system bus arbitration section, and Fig. 4. 1 is a signal diagram showing the transition of operation in a conventional example. 1...System bus, 2...System bus arbitration unit, 3...CPU0 (can request use of the system bus), 4...CPU1.5. ...
・・CPU2.61090. . CPU3.7-----・-Etberrhet, B
−・−・−DMA9・・・・・・1st block, 10・
...1 second block, 11...3rd block,
12-1...System bus use request signal (CP
Uo), 12-2...System bus use permission signal (CPUo), 13-1...System path use request signal (CPU1), 13-2...System bus Usage permission signal (CPU1), 14-1...
・System bus use request signal (CPU2), 14-2・
...System bus use permission signal (CPU2), 1
5-1...System bus use request signal (CPU
3), 15-2...System bus use permission signal (CPUs), 16-1...System bus use request signal (Ethernet), 16-2-V7.
f Muhas use permission signal (Ethernet), 17-1
----: System hash use request signal (DMA), 1
7-2... System bus use permission signal (DMA
), 18...Intra-block arbitration unit (first block), 19...Intra-block arbitration unit (second block), 2o...Intra-block arbitration unit (third block) block), 21-1... System bus use request signal (
1st block), 21-2... System hash use permission signal (1st block), 22-1... shift, system hash use request signal (2nd) request signal (3rd block) ), 23-2... system bus use permission signal (third block), 24... bus requester section.

Claims (1)

[Claims] a system bus that transmits address data control signals; a system bus arbitration unit that manages the right to use the system bus; a block that includes a plurality of devices that share the system bus; and a block that includes the right to use the system bus of the block. 1. A system bus arbitration apparatus, comprising: a bus requester section that requests a bus, and an intra-block arbitration section that independently determines system bus usage rights within the block for devices within the block.