JPH02307150A - Decentralized arbitration system - Google Patents

Abstract

PURPOSE:To shorten the delay time due to the increase of connection units by dividing the buses into many groups and connecting the units (bus arbiters) to the bus groups for control of the bus using right. CONSTITUTION:Plural bus arbiters 10 are connected to a bus handler 3 so that the buses are divided into plural groups and the system constitution can be extended. Each arbiter 10 arbitrates the bus using right request signals (BRQ) of its follower units 12 and extracts only the BRQ having the highest priority to give it to the handler 3. The handler 3 receives the BRQ from its follower unit 2 or the arbiter 10 and gives a bus use grant signal to the unit 2 having the highest priority or the arbiter 10. As a result, the increase of the signal delay time due to the increase of units 12 can be prevented.

Description

[Detailed Description of the Invention] [Summary] With regard to a bus control method for a general-purpose system bus, the purpose of this invention is to reduce delay time due to an increase in the number of connected units and to ease restrictions on the number of units that can be connected to the bus. , a plurality of units connected to the system bus, a bus controller that is connected to the system bus and manages the right to use the bus, and a plurality of units that are connected to the bus/X controller and are subordinate to it. When a bus usage right request signal is input from a bus handler, it is output to the bus handler as one bus usage right request signal, and when a bus usage permission signal is given from the bus handler, it is sent to multiple units under itself. A plurality of bus arbiters are provided, each bus arbiter is connected to a plurality of units via a system bus, and the bus handler is configured to grant bus usage rights in descending order of priority. Regarding control, the bus arbiter is configured so that it can be treated as a unit.

[Field of Industrial Application] The present invention relates to a bus control method for a general-purpose system bus, and more specifically, a centralized arbitration method in which a unit for managing bus usage rights is provided in an information transfer bus used in an information processing device. The system is configured so that bus usage rights can be exchanged between the unit connected to the bus and the unit managing the bus, by sending and receiving a bus usage permission signal and a bus usage permission signal. Concerning bus control methods in systems.

[Prior Art] FIG. 4 is a configuration diagram showing an example of a conventional bus system. In a general-purpose bus system in a computer system, a plurality of units 2 connected to a system bus 1 (hereinafter simply referred to as a bus) need to obtain the right to use the bus when transferring data using the bus 1. be. In order to obtain the right to use the bus, the unit 2 issues a bus handler (BH) 3 that manages the right to use the bus.
Bus request BQ, which is a bus usage right request signal for
Issue R. The bus handler 3 that receives this signal BQR issues a bus ground signal BGR, which is a bus usage permission signal, to the unit 2 that issued the signal. Only after the unit receives this BGR signal is it permitted to use the bus and can it use the bus.

FIG. 5 is a block diagram of the bus handler in FIG. 4. The bus handler 3 has a built-in arbitration circuit 3a that adjusts the bus, and receives bus usage right request signals BRQ-1 to BRQ-6 from a plurality of units 2, and selects the bus usage right request signals BRQ-1 to BRQ-6 from the units with the highest priority. Bus use permission signals BGR-1 to BGR-6 are provided.

When the arbitration circuit 3a receives the data transfer end signal BCPT from the unit 2, it outputs a bus use permission signal BGR to give the next unit 2 the right to use the bus.

[Problems to be Solved by the Invention] Incidentally, in a computer system configured by a plurality of units 2, a situation may occur in which BRQ signals are issued from the plurality of units 2 at the same time. The priority of unit 2 is checked and a BGR signal is given to unit 2 having a higher priority. Therefore, the bus handler 3 receives bus usage right request signals issued from all the units 2 connected to the bus 1, and the bus handler 3 also sends a signal to all the units 2 to permit use of the bus 1. is output.

In the conventional example, when attempting to greatly expand the scale of the system, unit 2 was connected to bus 1 and bus handler 3
It is necessary to connect the bus 1 usage right request signal and the bus usage permission signal to the bus 1. In the conventional examples shown in Figures 4 and 5, 13 signal lines are used to manage the right to use the bus to which six units are connected, but the system configuration becomes larger. As the number of units connected to bus 1 increases, the number of signal lines required to manage the right to use bus 1 increases.

However, there is a limit to the number of units that can be connected to the bus 1 due to a limit in the number of pins of connectors etc. that connect the bus 1, and therefore there is a problem in that the scale of the system cannot be increased beyond a certain level.

Furthermore, as the number of units increases, the bus arbitration circuit (arbitration circuit 3a) in the bus handler 3 becomes larger, and the amount of hardware increases. Moreover, as the circuit becomes larger, the delay time of the signal also increases.

In view of these points, the present invention divides the bus into several groups and connects a unit (bus arbiter) that manages the right to use the bus in each bus group, thereby dividing the arbitration circuit and delaying the bus. It is an object of the present invention to provide a distributed arbitration method that can reduce the time required and further ease the restriction on the number of units that can be connected to a bus by allowing bus handlers to manage their bus arbiters.

[Means for Solving the Problems] FIG. 1 is a block diagram of the principle of the present invention. Components that are the same as those in FIG. 4 are designated by the same reference numerals. In the figure, system bus 1. A plurality of units 2 connected to the bus 1
The bus handler 3 that controls the bus usage rights of these units 2 is the same as that shown in FIG. 10 is connected to the bus handler 3, and when a bus usage right request signal is input from a plurality of units under its own control, it outputs this as a bus usage right request signal to the bus handler 3, and When a bus use permission signal is given from the handler 3, the bus arbiter gives the right to use the bus to a plurality of units under itself in order of priority.

A plurality of these bus arbiters 10 are provided, a system bus 11 is connected to each bus arbiter 10, and a plurality of units 12 are connected to the system bus 11.

[Operation] In such a configuration, by connecting the bus arbiter 10 to the bus handler 3, the bus can be divided into a plurality of groups for use, and the system configuration can be expanded. Each bus arbiter 10 arbitrates the bus usage right request signals BRQ of the units 12 under its control, extracts only the BRQ signal with the highest priority, and provides it to the bus handler 3. When the bus handler 3 receives a bus use right request signal from the unit 2 or bus arbiter 10 under its control, it gives a bus use permission signal to the unit 2 or bus arbiter 10 with the highest priority.

Note that the bus handler 3 does not see the units 12 under the bus arbiter 10, but views all the units 12 under the bus arbiter 10 as one unit. Therefore, to the bus handler 3, no matter how many units 12 are connected under the bus arbiter 10, it appears that the number has increased only by the number of bus arbiters 10.

With this configuration, it is possible to prevent an increase in signal time delay due to an increase in the number of units, and even if the number of units increases, the number of signal lines does not increase as much as in the conventional example.
The system can be easily expanded.

[Embodiment] FIG. 2 is a block diagram showing an embodiment of a bus arbiter according to the distributed arbitration method of the present invention. In the figure, BUF1 to BUF15 are buffers inserted in each signal line, 21 is an arbitration circuit, and 22 is an OR (
OR) circuit.

The arbitration circuit 21 receives bus right request signals BRQ-1 to BRQ-6 from each subordinate unit, a bus permission signal BGR-E from the bus handler, and a data transfer end signal BCPT from the unit.

Additionally, a bus use permission signal can be output to each unit.

The OR circuit 22 ORs the six bus right request signals and outputs one bus right request signal BRQ-E to the bus handler.

When the bus use permission signal BGR-E is received from the bus handler, the arbitration circuit 21 selects the bus use right request issued from the subordinate units with the highest priority (priority is predetermined for each unit). Based on this, it is possible to know the unit with the highest priority that has issued a bus usage right request) bus usage permission signal (BGR-1
~BGR-6). After that, when the data transfer end signal BCPT is returned from the unit (in this case, the processing of the unit is assumed to be data transfer processing), a bus use permission signal is given to the remaining units that have issued the bus use right request signal. , similarly waits for the arrival of a data transfer end signal. When the bus right request signal disappears, the bus right request signal from the OR circuit 2 disappears. This allows the bus handler to know that the request has disappeared.

FIG. 3 is a block diagram showing one embodiment of the bus handler. In the figure, BUF11 to BUF27 are buffers inserted in each signal line, and 31 is an arbitration circuit. The arbitration circuit 31 receives bus usage right request signals BRQ-1 to BRQ- from the six subordinate units.
6 and the bus right request signal BRQ from the bus arbiter.
-E1゜BRQ-E2 is input, bus use permission signals BGR-1 to BGR-6 are input to each subordinate unit, and two bus use permission signals BGR-
It is configured to be able to output El and BGR-E2. Further, a data transfer end signal BCPT, which has been previously ORed externally (the circuit for ORing is not shown), is input from each subordinate unit and each bus arbiter.

When the arbitration circuit 31 receives bus use right request signals from subordinate units and bus arbiters, it sends out bus use permission signals to those with higher priority.

When dealing with subordinate units, use BGR-1 or BGR.
-6, and when it is directed to the bus arbiter, it outputs either BGR-El or BGR-E2. After that, when the data transfer end signal BCPT is returned, if there are any remaining bus use right request signals, a bus use permission signal is issued in response to the remaining bus use right request signals.

Note that data transfer between arbitrary units is of course possible, although bus acquisition and management by a bus handler are required.

[Effects of the Invention] As explained above, according to the present invention, by dividing the bus, the amount of hardware for a unit (bus handler or bus arbiter) that manages one bus can be reduced, and the amount of hardware can be increased. This can prevent the increase in time delay that would otherwise occur. Furthermore, it is easy to make the system configuration large-scale, and the system can be expanded over a wide range by considering the expanded bus arbiter and the units under the bus arbiter as one casing.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention. FIG. 2 is a block diagram showing an embodiment of a bus arbiter according to the distributed arbitration method of the present invention. FIG. 3 is an implementation of a bus handler according to the distributed arbitration method of the present invention. FIG. 4 is a block diagram showing an example of a conventional bus system. FIG. 5 is a block diagram of a bus handler in FIG. 4. In FIG. 1, 1.11 is a system bus, 2.12 is a unit, 3 is a bus handler, and 10 is a bus handler.

Claims (1)

[Claims] A centralized arbitration method in which a unit is provided to manage the right to use the bus in an information transfer bus used in an information processing device, and the right to use the bus is managed by the units connected to the bus and the bus. In a system configured to be able to monopolize the bus by sending and receiving a bus usage right request signal and a bus usage permission signal between the units connected to the system bus (1) and the system bus (1), multiple units (
2), a bus handler (3) that is connected to the system bus (1) and manages bus usage rights, and a bus handler (3) that is connected to the bus handler (3) and requests bus usage rights from multiple units under itself. When the signal is input from the bus handler (3), it is output as one bus usage right request signal to the bus handler (3), and when the bus handler (3) gives the bus usage permission signal, it outputs it to the bus handler (3). A plurality of bus arbiters (10) are provided which give bus usage rights to units in descending order of priority, and each bus arbiter (10) is connected to a plurality of units (12) via a system bus (11). A distributed arbitration method, characterized in that the bus handler (3) is configured to treat the bus arbiter (10) as a unit when it comes to controlling bus usage rights.