JP4288014B2 - Bus arbitration system and method - Google Patents

Description

【００３６】
ＤＳＰ０からの優先順位指定信号S0,S1,S2により、それぞれＤＳＰ０及び１とＤＳＰ２及び３との優先順位,ＤＳＰ０とＤＳＰ１との優先順位,ＤＳＰ２とＤＳＰ３との優先順位を任意に指定することができる。例えば、図６(ａ),(ｂ)に示した画像データの入力において、ＤＳＰ１が１０ライン分の画素データをＦＩＦＯメモリ１４から読み出している間はＤＳＰ１の優先順位を最高位にし、バスへのアクセス許可をＤＳＰ１に固定しておくことができる。ＤＳＰ１が１０ライン分の画素データを読み出した場合、ＤＳＰ０は、ＤＳＰ２の優先順位を最高位に設定する。または、ＤＳＰ１の優先順位を最高位にしたとき、ＤＳＰ２の優先順位を２番目に高い順位に設定する。
【００３７】
優先順位の設定は、バスを介さずにＤＳＰ０から直接バス・アービター１２に要求する。バス・アクセス要求及びバス・アクセス許可は、ＤＳＰとバス・アービター１２間でバスを介さず直接やり取りされる。バスへのアクセス許可は、バスへのアクセス要求が入力されてから１クロック以内に出力される。バスを介さず任意の優先順位を設定することで、システム全体のスループットを向上させることができる。
【００３８】
以上、本発明の一実施例について説明したが、本発明はその他の態様でも実施し得るものである。例えば、ＤＳＰが８個の場合は、図７に示すように、２つのＤＳＰを１組とし、２つの組を１つのグループとする。ユニット０にＤＳＰ０,１を接続し、ユニット１にＤＳＰ２,３を接続し、ユニット２にＤＳＰ４,５を接続し、ユニット３にＤＳＰ６,７を接続する。ユニット０,１を１グループにしてユニット４に接続し、ユニット２,３を１グループにしてユニット５に接続する。ユニット６にユニット４,５を接続する。
【００３９】
ＤＳＰ０とＤＳＰ１の選択は信号S3で、ＤＳＰ２とＤＳＰ３の選択は信号S4で、ＤＳＰ４とＤＳＰ５の選択は信号S5で、ＤＳＰ６とＤＳＰ７の選択は信号S6でそれぞれ行う。ユニット０とユニット１の選択は信号S1で、ユニット２とユニット３の選択は信号S2で、ユニット４とユニット５の選択は信号S0でそれぞれ行う。
【００４０】
以上、本発明は特定の実施例について説明されたが、本発明はこれらに限定されるものではない。本発明はその趣旨を逸脱しない範囲で当業者の知識に基づき種々なる改良，修正，変形を加えた態様で実施できるものである。同一の作用又は効果が生じる範囲内で、いずれかの発明特定事項を他の技術に置換した形態で実施できるものである。一体に構成されている発明特定事項を複数の部材から構成した形態でも、複数の部材から構成されている発明特定事項を一体に構成した形態でも実施できるものである。
【００４１】
【発明の効果】
本発明によれば、優先順位を指定する信号により、バスへのアクセスを許可するデバイスを二者択一方式で選択することができる。最高位の優先順位を与えるデバイスを任意に変更することができる。最高位以外の優先順位についても、二者択一の範囲内で各デバイスに任意の順位を与えることができる。バスを介さずに優先順位の指定及びバスへのアクセス許可を与えることができる。
【図面の簡単な説明】
【図１】本発明に係るバス調停システムの一構成例を示すブロック図である。
【図２】図１に示すバス・アービターの一構成例を示すブロック図である。
【図３】図２に示すユニット０,１,２の一構成例を示すブロック図である。
【図４】図１に示すＤＳＰの優先順位指定信号の出力インターフェイスの一構成例を示すブロック図である。
【図５】図４に示すユニットＢの一構成例を示すブロック図である。
【図６】 (ａ)は画像データの入力の概要を示す図であり、(ｂ)は１ラインごとのデータ入力とバスへアクセスするＤＳＰの一例を示す図である。
【図７】８個のＤＳＰを対象とした本発明に係るバス調停システムの一構成例を示すブロック図である。
【図８】従来のバス調停システムの一構成例を示すブロック図である。
【符号の説明】
１０：バス調停システム
１２：バス・アービター
１４：ＦＩＦＯメモリ
１６：ＰＣＩブリッジ
２０：アクセス要求を選択する回路
２２,２４,４２,５２：ＤＦＦ
３０：ユニット０,１,２の回路
３２：ＯＲ回路
３４：ＡＮＤ回路
３６,５６：インバータ回路
３８：二者択一回路
４０：出力インターフェイス
５０：ユニットＢの回路
５４：ＸＯＲ回路
６０：画像
６２：ラインＣＣＤ
７０：従来のバス調停システム
７２：従来のバス・アービター[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bus arbitration system and method when requests for access to a bus from a plurality of devices occur simultaneously, and more particularly to a bus arbitration system and method for arbitrating access to a bus of a plurality of processing units.
[0002]
[Prior art]
When high-speed calculation capability such as image processing is required, distributed processing is often performed by connecting a plurality of calculation processing devices to a common bus. Since there is only one bus, a plurality of arithmetic processing units cannot access the bus at the same time. When a bus access request is issued simultaneously from a plurality of arithmetic processing units, only one arithmetic processing unit is permitted to access the bus using a bus arbiter (bus arbitration unit). The bus arbiter gives an access permission to one arithmetic processing unit based on the priority of access to the bus of each arithmetic processing unit. The priority order is stored in a register in the bus arbiter, for example.
[0003]
The priority order may be fixed or switched in order. When the priority order is fixed, there is a possibility that an arithmetic processing unit with a low priority order cannot access the bus at all. When switching the priority order in order, when the priority order is the highest, the priority order is the lowest. A high priority cannot be continuously given to a specific arithmetic processing unit.
[0004]
The priority can be made variable by requesting the bus arbiter to change its priority. A signal requesting the change of priority is transmitted via the bus. Since only one arithmetic processing unit can access the bus at the same time, it is not possible to request the bus arbiter to change the priority while another device occupies the bus. The priority change often involves a waiting time until the bus is released.
[0005]
An example of a bus arbitration system 70 using bus arbiter (BUS ARBIT E R) shown in FIG. 8. Four DSPs (Digital Signal Processors) 0, 1, 2, and 3 are connected to a local bus (LOCAL BUS: hereinafter simply referred to as a bus). A bus arbiter 72, a FIFO memory (First In First Out MEMORY) 14, and a PCI bridge (Peripheral Component Interconnect BRIDGE) 16 are connected to the bus. For example, image data is input to the FIFO memory 14, and the DSPs 0, 1, 2, and 3 read out the image data from the FIFO memory 14 and perform arithmetic processing. The PCI bridge controls connection between the local bus and the PCI bus (PCIBUS).
[0006]
In this description, the bus arbitration in the case where the DSPs 0, 1, 2, and 3 read image data from the FIFO memory 14 will be described as an example. Of course, when a device (not shown) connected to the PCI bus accesses the FIFO memory 14, a bus access request is sent from the PCI bridge 16 to the bus arbiter 72. The DSP can use any arithmetic processing unit such as an MPU (Microprocessor Unit).
[0007]
Image data is input to the FIFO memory 14, and the DSPs 0, 1, 2, and 3 read the image data from the FIFO memory 14 and perform arithmetic processing. For example, in the case of image input by an image scanner, an image 60 is read by moving a linear CCD (Charge Coupled Device) 62 in parallel as shown in FIG. Since the linear CCD 62 is used, image data is input to the FIFO memory 14 in units of pixel data for one line. Each DSP reads, for example, pixel data for 10 lines from the FIFO memory 14 and performs arithmetic processing. For example, arithmetic processing for pixel data for the first 10 lines is performed by DSP1, and arithmetic processing for pixel data for the next 10 lines is performed by DSP2.
[0008]
Since the pixel data is input to the FIFO memory 14 in units of one line, for example, as shown in FIG. 6B, a temporary empty time may occur in the pixel data transfer from the FIFO memory 14 to the DSP 1. If the bus is not in use, the right to access the bus is transferred to another DSP requesting access to the FIFO memory 14. However, since the input of pixel data from the linear CCD 62 is continued, it is necessary to reassign the access right to the DSP 1. If the access right is passed to another DSP, the DSP 1 cannot access the FIFO memory 14 until the other DSP to which the access right is passed releases the bus.
[0009]
[Problems to be solved by the invention]
An object of the present invention is to reduce the waiting time for accessing the bus of the device having the highest priority.
[0010]
Another object of the present invention is to dynamically give the highest priority to any device.
[0011]
[Means for Solving the Problems]
The bus arbitration system of the present invention includes (a) priority designation means for generating a signal for designating the priority of access to a bus of a device, and (b) each device and priority designation means connected to each other. And a bus arbiter that grants access permission to any of the devices that have requested access to the bus according to the designated signal. Such a bus arbitration system can give priority designation and access permission to the bus without going through the bus. The device with the highest priority can be arbitrarily changed by means for designating the priority.
[0012]
The bus arbitration method of the present invention includes: (a) a step of designating priority of each device; (b) a step of requesting access from each device to the bus; and (c) a device requesting access to the bus. Selecting a device from which access to the bus is permitted based on the priority, and (d) permitting the selected device to access the bus.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
Next, embodiments of a bus arbitration system and an arbitration method according to the present invention will be described in detail based on the drawings. As shown in FIG. 1, five devices (DSPs 0, 1, 2, 3, and PCI bridge 16) are connected to a local bus (hereinafter simply referred to as a bus). Although an access request to the bus from the PCI bridge 16 also occurs, the arbitration of access to the bus for the four DSPs 0, 1, 2, and 3 will be described as an example. The DSPs 0, 1, 2, 3, the PCI bridge 16, and the FIFO memory 14 are assumed to be the same as in the prior art.
[0014]
The DSPs 0, 1, 2, and 3 perform arithmetic processing on image data input from the line CCD 62 shown in FIG. Arithmetic processing for pixel data for every 10 lines input from the line CCD 62 to the FIFO memory 14 is assigned to the DSPs 0, 1, 2, and 3 and executed. The DSP 0 performs control of distributed processing such as data allocation to the DSPs 0, 1, 2, and 3. Designation of the priority order of each DSP0, 1, 2, 3 is performed by DSP0.
[0015]
The bus arbiter 12 is directly connected to the DSPs 0, 1, 2, and 3 without a bus. DSPs 0, 1, 2, and 3 send bus request signals BREQ0, 1, 2, and 3 to the bus arbiter 12, respectively. Bus access grant signals GRA0, 1, 2, and 3 are sent from the bus arbiter 12 to the DSPs 0, 1, 2, and 3, respectively.
[0016]
The DSP 0 that specifies the priority order of the DSPs 0, 1, 2, and 3 is directly connected to the bus arbiter 12 without a bus. Signals S0, S1, and S2 that specify the priority order are sent from the DSP0 to the bus arbiter 12.
[0017]
The bus arbiter 12 selects one access request signal from the access request signals BREQ0, 1, 2, and 3 input from the DSPs 0, 1, 2, and 3 based on the priority order input from the DSP0. The access permission signal is output to the DSP that has output the selected access request signal. An example of a circuit for selecting an access request signal in the bus arbiter 12 is shown in FIG.
[0018]
The circuit 20 shown in FIG. 2 selects two access devices as a set of two devices. In this description, DSP0 and DSP1 are one set, and DSP2 and DSP3 are one set. DSP0 and DSP1 are connected to unit (UNIT) 0, and DSP2 and DSP3 are connected to unit 1. Furthermore, in the circuit 20 shown in FIG. 2, two units are grouped into one group and an access request is selected. In this description, unit 0 and unit 1 are grouped together, and unit 0 and unit 1 are connected to unit 2.
[0019]
Units 0, 1, and 2 are identical. An example of the circuit configuration of units 0, 1, and 2 is shown in FIG. Reference numeral 32 in the figure is an OR circuit, reference numeral 34 is an AND circuit, reference numeral 36 is an inverter circuit, and reference numeral 38 is an alternative circuit. The alternative circuit 38 has 1Y = 1A and 4Y = 4A when S is LOW (“0”), and 1Y = 1B and 4Y = 4B when S is High (“1”).
[0020]
When a signal is input to H0 and / or H1, a signal is output from HOUT. When a signal is input to AIN, the signal can be output from either A0 or A1. A signal is output from A0 if there is an input only to H0, and a signal is output from A1 if there is an input only to H1. When both H0 and H1 have inputs, A0 and A1 are selected according to the signal input to S. For example, when no signal is input to S (S = "0"), A0 is selected, and when a signal is input to S (S = "1"), A1 is selected. When a signal is input to QA0 and / or QA1, a signal is output from QAOUT.
[0021]
As shown in FIG. 2, a bus access request signal BREQ0 from DSP0 is input to H0 of unit 0 via a D-type flip-flop (hereinafter referred to as DFF) 22, and a bus access request signal BREQ1 from DSP1. Is input to H1 of unit 0 via DFF22. When an access request signal is input to either or both of DSP0 and DSP1, a signal is sent from HOUT of unit 0 to H0 of unit 2. Unit 2 can detect the presence / absence of an access request from DSP0 and DSP1 based on a signal from HOUT of unit 0. The DFF 22 can control the input timing of the access request signals BREQ0, 1 with the clock signal CLK.
[0022]
An access permission signal GRA0 to DSP0 is output from A0 of unit 0 through DFF24, and an access permission signal GRA1 to DSP1 is output from A1 of unit 0 through DFF24. The access permission signal GRA0 or GRA1 can be output only when a signal is sent from A0 of unit 2 to AIN of unit 0. Unit 2 can authorize an access request from DSP0 or DSP1 by sending a signal to the AIN of unit 0.
[0023]
When a signal is input to AIN, unit 0 can output access permission signal GRA0 or GRA1. When only H0 has an input, A0 to GRA0 are output, and when only H1 has an input, A1 to GRA1 are output. When both H0 and H1 have inputs, GRA0 or GRA1 is selected according to the signal S1 input from DSP0 to S of unit 0. In this description, if no signal is input to S (S1 = "0"), GRA0 is output from A0, and if a signal is input to S (S1 = "1"), GRA1 is output from A1 To do. DSP0 can select either DSP0 or DSP1 by a signal S1 input to S of unit 0. The DFF 24 can control the switching timing of the access permission signal with the clock signal CLK.
[0024]
The bus access permission signals GRA0 and GRA1 are also input to QA0 and QA1 of unit 0, respectively. Unit 0 can recognize the DSP that is permitted to access the bus from the signals input to QA0 and QA1. When a signal is input to QA0 or QA1, a signal is output from QAOUT of unit 0 to QA0 of unit 2. Unit 2 can recognize that access to the bus from DSP0 or DSP1 is permitted by a signal output from QAOUT of unit 0.
[0025]
As for DSP2 and DSP3, similarly to DSP0 and DSP1, bus access request signals BREQ2 and BREQ3 from DSP2 and DSP3 are respectively input to H0 and H1 of unit 1 via DFF22. Bus access permission signals GRA2 and GRA3 to the DSP2 and DSP3 are output from the A0 and A1 of the unit 1 via the DFF 24, respectively. The signal S2 output from DSP0 is input to S of unit 1. The bus access permission signals GRA2 and GRA3 are also input to QA0 and QA1 of the unit 1, respectively.
[0026]
The units 0 and 1 are connected to the unit 2 in the same manner as the connections of the DSPs 0 and 1 to the unit 0 and the DSPs 2 and 3 to the unit 1. The signal output from HOUT of unit 0 is input to H0 of unit 2, and the signal output from HOUT of unit 1 is input to H1 of unit 2. From the signals input to H0 and H1, the unit 2 can recognize the presence / absence of an access request to each of the units 0 and 1.
[0027]
A signal input to AIN of unit 0 is output from A0 of unit 2, and a signal input to AIN of unit 1 is output from A1 of unit 2. Since the signal is always input to the AIN of the unit 2, the signal can be output from either A0 or A1. A signal is output from A0 if there is an input only to H0, and a signal is output from A1 if there is an input only to H1. When there is an input to H0 and H1, either A0 or A1 is selected according to the signal S0 input from DSP0 to S. In this description, A0 is selected when no signal is input to S (S0 = "0"), and A1 is selected when a signal is input to S (S0 = "1").
[0028]
The signal output from QAOUT of unit 0 is input to QA0 of unit 2, and the signal output from QAOUT of unit 1 is input to QA1 of unit 2. From the signals input to QA0 and QA1, unit 2 can recognize that either unit 0 or unit 1 is connected to a DSP that is permitted to access the bus.
[0029]
FIG. 4 shows an example of an output interface of signals S0 and S1.S2 that specify the priority order sent from the DSP 0 to the bus arbiter 12. In FIG. S0 is a signal input to the unit 2, S1 is a signal input to the unit 0, and S2 is a signal input to the unit 1. The priority specification signals S1, S2, S3 output from the DSP0 are input to the unit A including four DFFs. A signal CHG for operating the output interface 40 is input to the unit A via the FDD 42 and the unit B. With the unit A, the input timing of the priority order of each device can be controlled by the clock signal CLK.
[0030]
An example of the circuit configuration of unit B is shown in FIG. Reference numeral 52 denotes a DFF, reference numeral 54 denotes an XOR circuit, and reference numeral 56 denotes an inverter circuit. Unit B outputs a pulse at the rise and fall of the output signal of DFF42. The pulse output from unit B is input to unit A, and instructions for rewriting the four DFFs included in unit A are given. The circuits shown in FIGS. 2 to 5 described above can be mounted on a rewritable gate array.
[0031]
Next, the operation of the bus arbitration method using the bus arbitration system of the present invention will be described.
[0032]
When an access request to the bus is generated from either or both of DSP0 and DSP1, a signal is output from HOUT of unit 0 to H0 of unit 2. Similarly, when an access request to the bus is generated from either or both of DSP2 and DSP3, a signal is output from HOUT of unit 1 to H1 of unit 2.
[0033]
Unit 2 sends a signal from A0 to AIN of unit 0 when only H0 has an input. Similarly, unit 2 sends a signal from A1 to AIN of unit 1 when there is an input only to H1. When signals are input to both H0 and H1, a signal is output from either A0 or A1 based on the signal S0 input to S. Either unit 0 (including DSPs 0 and 1) or unit 1 (including DSPs 2 and 3) is selected by the signal S0.
[0034]
When a signal is input to AIN, unit 0 outputs a signal from A0 if there is an input only to H0, and outputs a signal from A1 if there is an input only to H1. When both H0 and H1 have inputs, a signal is output from either A0 or A1 based on the signal S1 input to S. Either DSP0 or DSP1 is selected by the signal S1. When a signal is input to the AIN of the unit 1, the same operation as that of the unit 0 described above is performed.
[0035]
Table 1 shows the relationship between the signals S0, S1, S2 and the priorities of the DSPs 0, 1, 2, 3 in the circuit 20 shown in FIG. The priority is 4 for the highest priority and 1 for the lowest.
[Table 1]

[0036]
Priority designation signals S0, S1 and S2 from DSP0 can arbitrarily designate the priority between DSP0 and DSP1 and DSP2 and 3, respectively, the priority between DSP0 and DSP1, and the priority between DSP2 and DSP3. . For example, in the input of the image data shown in FIGS. 6A and 6B, while the DSP 1 is reading out the pixel data for 10 lines from the FIFO memory 14, the DSP 1 is given the highest priority, The access permission can be fixed to the DSP 1. When the DSP 1 reads pixel data for 10 lines, the DSP 0 sets the priority order of the DSP 2 to the highest. Alternatively, when the priority order of DSP1 is made highest, the priority order of DSP2 is set to the second highest order.
[0037]
The priority order is requested directly from the DSP 0 to the bus arbiter 12 without going through the bus. The bus access request and the bus access permission are directly exchanged between the DSP and the bus arbiter 12 without using the bus. The bus access permission is output within one clock after the bus access request is input. By setting an arbitrary priority without going through the bus, the throughput of the entire system can be improved.
[0038]
As mentioned above, although one Example of this invention was described, this invention can be implemented also in another aspect. For example, when there are eight DSPs, as shown in FIG. 7, two DSPs are set as one set, and two sets are set as one group. DSPs 0 and 1 are connected to unit 0, DSPs 2 and 3 are connected to unit 1, DSPs 4 and 5 are connected to unit 2, and DSPs 6 and 7 are connected to unit 3. Units 0 and 1 are grouped and connected to unit 4, and units 2 and 3 are grouped and connected to unit 5. Units 4 and 5 are connected to unit 6.
[0039]
DSP0 and DSP1 are selected by signal S3, DSP2 and DSP3 are selected by signal S4, DSP4 and DSP5 are selected by signal S5, and DSP6 and DSP7 are selected by signal S6. Unit 0 and unit 1 are selected by signal S1, units 2 and 3 are selected by signal S2, and units 4 and 5 are selected by signal S0.
[0040]
As mentioned above, although this invention was demonstrated about the specific Example, this invention is not limited to these. The present invention can be implemented in variously modified, modified, and modified forms based on the knowledge of those skilled in the art without departing from the spirit of the present invention. The invention can be implemented in a form in which any one of the invention-specific matters is replaced with another technique within a range where the same action or effect occurs. The invention specific matter constituted integrally may be implemented by a form constituted by a plurality of members, or the invention specific matter constituted by a plurality of members may be implemented integrally.
[0041]
【The invention's effect】
According to the present invention, a device that permits access to a bus can be selected by a two-way selection method using a signal that designates priority. The device that gives the highest priority can be arbitrarily changed. With regard to priorities other than the highest level, any order can be given to each device within a range of alternatives. Specification of priority and access permission to the bus can be given without going through the bus.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration example of a bus arbitration system according to the present invention.
FIG. 2 is a block diagram showing a configuration example of a bus arbiter shown in FIG.
3 is a block diagram showing an example of the configuration of units 0, 1, and 2 shown in FIG.
4 is a block diagram showing a configuration example of an output interface of a DSP priority order designation signal shown in FIG. 1;
5 is a block diagram showing an example of the configuration of unit B shown in FIG.
6A is a diagram showing an outline of image data input, and FIG. 6B is a diagram showing an example of a DSP that accesses data input and buses for each line.
FIG. 7 is a block diagram showing an example of the configuration of a bus arbitration system according to the present invention targeting eight DSPs.
FIG. 8 is a block diagram showing a configuration example of a conventional bus arbitration system.
[Explanation of symbols]
10: Bus arbitration system 12: Bus arbiter 14: FIFO memory 16: PCI bridge 20: Circuits 22, 24, 42, 52 for selecting access requests: DFF
30: Circuit of units 0, 1, 2 32: OR circuit 34: AND circuit 36, 56: Inverter circuit 38: Alternative circuit 40: Output interface 50: Circuit of unit B 54: XOR circuit 60: Image 62: Line CCD
70: Conventional bus arbitration system 72: Conventional bus arbiter

Claims (10)

Multiple devices connected to a common bus,
Priority specifying means for generating a signal for specifying the priority of access to the bus of the device;
A bus arbiter connected to each of the devices and the priority designation means, and granting access permission to any of the devices that have requested access to the bus in response to a signal designating the priority;
The bus arbiter
Set two devices as one set, and for each set,
Two input terminals to which access requests output from two devices are respectively input;
Two output terminals for respectively outputting access permission to two devices within one clock after the access request is input;
A second output terminal for outputting an access request from one or both of the two devices;
A second input terminal to which an access permission based on the priority is input in response to an access request from one or both of the two devices;
A third input terminal to which a signal for selecting one of access requests from two devices based on the priority is input from the priority specifying means;
The bus arbitration system, wherein the priority designation means is in one of the plurality of devices. The bus arbiter
Two groups are grouped together, and for each group,
Two input terminals to which access requests from two sets of the second output terminals are respectively input;
Two output terminals that respectively output access permission to the two sets of the second input terminals;
A fourth output terminal for outputting an access request from one or both of the two sets;
A fourth input terminal to which an access permission based on the priority order is input to an access request from one or both of the two sets;
The bus arbitration system according to claim 1, further comprising a fifth input terminal to which a signal for selecting one of the access requests from the two sets based on the priority is input. When there are a plurality of the groups, the two groups are further combined into one group,
3. The bus arbitration system according to claim 2, wherein each group includes two groups or two sets.   4. The bus arbitration system according to claim 1, wherein the bus arbiter includes means for aligning input timings of access requests of the devices and means for aligning output timings of access permission to the devices. A method of arbitrating access to a bus of a plurality of devices connected to a common bus,
A step of specifying the priority of each device by the priority specifying means;
Requesting access to the bus from each device;
Selecting a device from which access to the bus is permitted based on the priority order from among devices that have requested access to the bus;
Allowing access to a bus to the selected device;
The step of selecting comprises:
Set two devices as one set, and for each set,
Detecting an access request from one or both of the two devices;
Selecting one of the two devices based on the priority;
Allowing access based on the priority for access requests from one or both of the two devices within one clock of detecting the access request,
A bus arbitration method in which the step of specifying the priority order of each device is performed by a priority order specifying means provided in one of the plurality of devices. Selecting one of the two devices comprises:
When only one of the two devices is requesting access to the bus, selecting the device requesting access;
6. The bus arbitration method of claim 5, further comprising the step of selecting the higher priority device when both of the two devices are requesting access to the bus. The step of selecting comprises:
Two groups are grouped together, and for each group,
Detecting an access request to one or both of the two sets;
Granting access based on the priority for an access request to one or both of the two sets;
The bus arbitration method according to claim 5, further comprising: selecting one of the two sets based on the priority. Designating one of the two sets comprises:
When only one of the two sets has an access request to the bus, the step of specifying the set with the access request;
The bus arbitration method according to claim 7, further comprising the step of designating a set including the device having the highest priority when both of the two sets have access requests to the bus. When there are a plurality of the groups, the two groups are further combined into one group,
9. The bus arbitration method according to claim 7, wherein each group includes two groups or two sets. Wherein the step of aligning the timing of detecting the access request, one of the bus arbitration method of claims 5 to 9 comprising the steps of: aligning the timing to allow the access.

Images