JP2002269030A - System and method for arbitrating bus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce waiting time for the designation of priority and the permission of access to a bus and to set arbitrary priority to respective devices. SOLUTION: A bus arbitrating system is provided with a bus arbiter 12 which is directly connected to the respective devices DSP0, 1, 2 and 3 without making them pass through a common bus (local bus) and which gives access permission to one of the devices requesting access to the bus based on priority which is set to the respective devices DSP0, 1, 2 and 3, and further provided with a means (DSP0) which is directly connected to the bus arbiter 12 without making it pass through the common bus and which designates the priority of the respective devices DSP0, 1, 2 and 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus arbitration system and method for simultaneously accessing a bus from a plurality of devices, and more particularly, to arbitrating access to a bus of a plurality of processing units. The present invention relates to a bus arbitration system and method.

[0002]

2. Description of the Related Art When a high-speed calculation capability such as image processing is required, a plurality of processing units are often connected to a common bus to perform distributed processing. Since there is one bus, a plurality of processing units cannot access the bus at the same time. When a request for access to the bus is issued simultaneously from a plurality of processing units, only one processing unit is permitted to access the bus using a bus arbiter (bus arbitration unit). The bus arbiter grants access to one processing unit based on the priority of each processing unit accessing the bus. The priority is stored in a register inside the bus arbiter, for example.

The priorities may be fixed or switched in order. When the priority is fixed, there is a possibility that an arithmetic processing unit having a low priority cannot access the bus at all. In the case where the priorities are sequentially switched, when the priority is the highest, the priority is next the lowest. It is not possible to keep giving high priority to a specific arithmetic processing unit.

The priority can be made variable by the arithmetic processing unit requesting the bus arbiter to change its priority. The signal requesting the priority change is transmitted via the bus. Since only one arithmetic processing unit can access the bus at the same time, it is not possible to request the bus arbiter to change the priority while another device occupies the bus. Changing the priority often involves waiting for the bus to be released.

FIG. 8 shows an example of a bus arbitration system 70 using a bus arbiter (BUS ARBITOR). local·
Four DSs on a bus (LOCAL BUS)
P (Digital Signal Processor) 0, 1, 2, 3 are connected. The bus has a bus arbiter 72 and a FIFO
Memory (First In First Out MEMORY) 14 and PCI Bridge (Peripheral Component Interconnect BRIDGE) 1
6 is connected. For example, image data is input to the FIFO memory 14, and DSPs 0, 1, 2, and 3
The image data is read from the memory 14 to perform the arithmetic processing. The PCI bridge consists of a local bus and a PCI bus (P
Controls connection with CI BUS).

In this description, DSPs 0, 1, 2, and 3 are FIF
A description will be given by taking bus arbitration when reading image data from the O memory 14 as an example. Of course, when a device (not shown) connected to the PCI bus accesses the FIFO memory 14, the PCI bridge 16 sends a bus access request to the bus arbiter 72. DS
For P, any arithmetic processing device such as an MPU (Microprocessor Unit) can be used.

Image data is input to the FIFO memory 14, and the DSPs 0, 1, 2, and 3 read out the image data from the FIFO memory 14 and perform arithmetic processing. For example, in the case of image input by an image scanner, as shown in FIG. 6A, an image 60 is read by moving a linear CCD (Charge Coupled Device) 62 in parallel. Linear CCD6
2, the image data is input to the FIFO memory 14 in units of one line of pixel data. Each DSP stores, for example, 10 lines of pixel data in a FIFO
The data is read from the memory 14 and arithmetic processing is performed. For example, the arithmetic processing for the first 10 lines of pixel data is performed by the DSP 1, and the arithmetic processing for the next 10 lines of pixel data is performed by the DSP 2.

Since pixel data is input to the FIFO memory 14 on a line-by-line basis, for example, as shown in FIG. 6B, a temporary idle time may occur in the transfer of pixel data from the FIFO memory 14 to the DSP 1. is there. If the bus is not used, the access right to the bus is transferred to another DSP requesting access to the FIFO memory 14. However, since the input of the pixel data from the linear CCD 62 is continued, it is necessary to reassign the access right to the DSP 1. If the access right is passed to another DSP, the DSP 1 cannot access the FIFO memory 14 until the other DSP to which the access right is passed releases the bus.

[0009]

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the waiting time for a device having the highest priority to access a bus.

Another object of the present invention is to dynamically assign the highest priority to any device.

[0011]

The bus arbitration system according to the present invention comprises: (a) a priority specifying means for generating a signal for specifying a priority of device access to the bus; and (b) each device and the priority. A bus arbiter connected to the specifying means and for granting access permission to any of the devices that have requested access to the bus in accordance with a signal specifying the priority. Such a bus arbitration system can give priority designation and access permission to the bus without passing through the bus. The device with the highest priority can be arbitrarily changed by the means for specifying the priority.

According to the bus arbitration method of the present invention, there are provided (a) a step of designating a priority order of each device, (b) a step of requesting each device to access the bus, and (c) a request of access to the bus. And (d) permitting the selected device to access the bus from the selected devices based on the priority.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of a bus arbitration system and an arbitration method according to the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, the local bus
(Hereinafter simply referred to as a bus) and five devices (DSP0,
1, 2, 3, and PCI bridges 16) are connected. PC
An access request from the I-bridge 16 to the bus also occurs,
Arbitration of access to the bus for the four DSPs 0, 1, 2, and 3 will be described as an example. The DSPs 0, 1, 2, 3, the PCI bridge 16, and the FIFO memory 14 are assumed to be the same as the conventional one.

The DSPs 0, 1, 2, and 3 perform arithmetic processing on image data input from the line CCD 62 shown in FIG. The arithmetic processing for the pixel data for every ten lines input from the line CCD 62 to the FIFO memory 14 is assigned to each of the DSPs 0, 1, 2, and 3 and executed. Control of distributed processing such as allocation of data to each of the DSPs 0, 1, 2, and 3 is performed by the DSP 0. Designation of the priorities of the DSPs 0, 1, 2, and 3 is performed by the DSP 0.

The bus arbiter 12 includes DSPs 0, 1,
It is directly connected to a few without passing through a bus. DSP0,
Bus access request signals BREQ0, 1, 2, and 3 are sent to the bus arbiter 12 from 1, 2, and 3, respectively. bus·
The arbiter 12 sends bus access permission signals GRA0, 1, 2, and 3 to the DSPs 0, 1, 2, and 3, respectively.

A DSP 0 for designating the priorities of the DSPs 0, 1, 2, and 3 is directly connected to the bus arbiter 12 without passing through a bus. Bus Arbiter 1 from DSP0
Signals S0, S1, and S2 for designating the priority are sent to 2.

The bus arbiter 12 selects one of the access request signals BREQ0, 1, 2, 3 inputted from each of the DSPs 0, 1, 2, 3 based on the priority inputted from the DSP 0.
One access request signal is selected, and an access permission signal is output to the DSP that has output the selected access request signal. FIG. 2 shows an example of a circuit in the bus arbiter 12 for selecting an access request signal.

The circuit 20 shown in FIG. 2 sets two devices as one set and selects an access request signal. In this description, DSP0 and DSP1 are set as one set, and DSP2 and DSP1 are
3 as one set. DSP0 and DSP1 are units (U
NIT) 0, and DSP2 and DSP3 are connected to unit 1. Further, in the circuit 20 shown in FIG. 2, the two units are grouped into one group, and an access request is selected. In this description, unit 0 and unit 1 are grouped together, and unit 0 and unit 1 are connected to unit 2.

The units 0, 1, 2 are identical. FIG. 3 shows a circuit configuration example of the units 0, 1, and 2. Reference numeral 32 in the figure
Is an OR circuit, reference numeral 34 is an AND circuit, reference numeral 36 is an inverter circuit, and reference numeral 38 is an alternative circuit. The alternative circuit 38 outputs 1Y = S when S is LOW ("0").
1A and 4Y = 4A, and when S is High ("1"), 1Y = 1B and 4Y = 4B.

When a signal is input to H0 and / or H1, HOU
A signal is output from T. When a signal is input to AIN, A0
Alternatively, a signal can be output from either A1 or A1. A signal is output from A0 if only H0 has an input, and a signal is output from A1 if only H1 has an input. If there is an input to both H0 and H1, A0 and A1 are selected according to the signal input to S. For example, if no signal is input to S (S = "0"),
If A0 is selected and a signal is input to S (S = "1")
A1 is selected. When a signal is input to QA0 and / or QA1, a signal is output from QAOUT.

As shown in FIG. 2, the bus from DSP0
The access request signal BREQ0 is input to H0 of the unit 0 via a D-type flip-flop (hereinafter, referred to as DFF) 22, and the bus access request signal BREQ1 from the DSP 1
It is input to H1 of unit 0 via FF22. DSP0
When an access request signal is input to one or both of the DSP 1 and the DSP 1, a signal is transmitted from HOUT of the unit 0 to H0 of the unit 2. Unit 2 can detect the presence or absence of an access request from DSP0 and DSP1 based on a signal from HOUT of unit 0. The DFF 22 determines the timing of inputting the access request signal BREQ0,1 by the clock signal C.
Can be controlled by LK.

The access permission signal GRA0 for DSP0 is output from A0 of unit 0 via DFF24,
Access permission signal GRA1 from A1 of unit 0 to DFF
24. Access permission signal GRA0 or GR
A1 can be output only when a signal is sent from A0 of unit 2 to AIN of unit 0. Unit 2 sends DSP0 or DS0 by sending a signal to AIN of unit 0.
An access request from P1 can be permitted.

When a signal is input to the AIN, the unit 0
Can output the access permission signal GRA0 or GRA1. When only H0 has an input, A0 outputs GRA0. When only H1 has an input, A1 outputs GRA1. If there is an input to both H0 and H1, GRA0 or GRA1 is selected according to the signal S1 input to S of unit 0 from DSP0. In this description, if no signal is input to S (S1 = "0"), A0 to G
RA0 is output, and if a signal is input to S (S1 = "1"), A1
To output GRA1. DSP0 can select either DSP0 or DSP1 according to signal S1 input to S of unit 0. With the DFF 24, the timing of switching the access permission signal can be controlled by the clock signal CLK.

The bus access permission signals GRA0 and GRA1 are also input to QA0 and QA1 of unit 0, respectively. The unit 0 can recognize the DSP that is permitted to access the bus from the signals input to QA0 and QA1. QA0
Alternatively, when a signal is input to QA1, a signal is output from QAOUT of unit 0 to QA0 of unit 2. Unit 2
By the signal output from QAOUT of unit 0, DSP
0 or that access to the bus from the DSP 1 is permitted.

For DSP2 and DSP3, DSP0
Buses from DSP2 and DSP3 as well as DSP1
The access request signals BREQ2 and BREQ3 are input to H0 and H1 of the unit 1 via the DFF 22, respectively. DSP2, DSP
The bus access permission signals GRA2 and GRA3 for the unit 3 are output from A0 and A1 of the unit 1 via the DFF 24, respectively. The signal S2 output from the DSP0 is input to S of the unit 1. The bus access permission signals GRA2 and GRA3 are also input to QA0 and QA1 of the unit 1, respectively.

The connection of units 0 and 1 to unit 2
The connection is performed in the same manner as the connection of the DSPs 0 and 1 to the unit 0 and the connection of the DSPs 2 and 3 to the unit 1. The signal output from HOUT of unit 0 is input to H0 of unit 2, and the signal output from HOUT of unit 1 is input to H1 of unit 2. The signals input to H0 and H1 cause the unit 2
Can recognize whether or not there is an access request to each of the units 0 and 1.

The signal input to AIN of unit 0 is output from A0 of unit 2, and the signal input to AIN of unit 1 is output from A1 of unit 2. Since a signal is always input to the AIN of the unit 2, a signal can be output from either A0 or A1. If only H0 has an input, a signal is output from A0, and if only H1 has an input, a signal is output from A1. When there are inputs to H0 and H1, either A0 or A1 is selected according to the signal S0 input from DSP0 to S. In this description, if no signal is input to S (S0 = "0"), A0 is selected and S
A1 is selected when a signal is input to the terminal (S0 = "1").

The signal output from QAOUT of unit 0 is input to QA0 of unit 2 and the signal output from QAOUT of unit 1 is input to QA1 of unit 2. Q
Based on the signals input to A0 and QA1, the unit 2 can recognize that one of the units 0 and 1 is connected to a DSP permitted to access the bus.

FIG. 4 shows an example of the output interface of the signals S0, S1 and S2 for specifying the priority sent from the DSP0 to the bus arbiter 12. S0 is a signal input to the unit 2, S1 is a signal input to the unit 0, and S2 is a signal input to the unit 1. DSP0
Priority designation signals S1, S2, S3 output from the four DFs
Input to unit A including F. A signal CHG for operating the output interface 40 is input to the unit A via the FDD 42 and the unit B. The unit A controls the input timing of the priority of each device by using a clock signal.
It can be controlled by CLK.

FIG. 5 shows an example of the circuit configuration of the unit B. Reference numeral 52 denotes a DFF, reference numeral 54 denotes an XOR circuit, and reference numeral 56 denotes an inverter circuit. Unit B is DFF4
The pulse is output at the rise and fall of the output signal of No. 2. The pulse output from the unit B is input to the unit A, and instructs rewriting of four DFFs included in the unit A. The circuits described above and shown in FIGS.
It can be implemented on a rewritable gate array.

Next, the operation of the bus arbitration method using the bus arbitration system of the present invention will be described.

When an access request to the bus is generated from one or both of DSP0 and DSP1, the HO of unit 0 is
A signal is output from the UT to H0 of the unit 2. Similarly, D
When an access request to the bus is generated from one or both of SP2 and DSP3, a signal is output from HOUT of unit 1 to H1 of unit 2.

The unit 2 sends a signal from A0 to the AIN of unit 0 when there is an input only at H0. Similarly, unit 2 sends a signal from A1 to AIN of unit 1 if there is an input only at H1. If a signal is input to both H0 and H1, A0 is determined based on the signal S0 input to S.
And output a signal from either A1. According to the signal S0, the unit 0 (including DSP0, 1) and the unit 1 (DSP2,
3).

When a signal is input to AIN, the unit 0 outputs a signal from A0 when only H0 has an input, and outputs a signal from H0.
If only the input is present, the signal is output from A1. H0 and H1
If both have inputs, a signal is output from either A0 or A1 based on the signal S1 input to S. Signal S1
Selects either DSP0 or DSP1. When a signal is input to the AIN of the unit 1, the same operation as that of the unit 0 is performed.

Table 1 shows the relationship between the signals S0, S1, S2 in the circuit 20 shown in FIG. 2 and the priorities of the DSPs 0, 1, 2, and 3. As for the priority, 4 is the highest and 1 is the lowest.

[Table 1]

Priority designation signals S0, S1, S2 from DSP0
Thus, the priorities of DSP0 and DSP1 and DSP2 and DSP3, the priority of DSP0 and DSP1, and the priority of DSP2 and DSP3 can be arbitrarily specified.
For example, when inputting the image data shown in FIGS. 6A and 6B, the DSP 1
While the data is being read from the memory 14, the priority of the DSP 1 can be set to the highest priority, and the access permission to the bus can be fixed to the DSP 1. When DSP1 has read out the pixel data for 10 lines, DSP0 sets the priority of DSP2 to the highest. Alternatively, when the priority of DSP1 is the highest, the priority of DSP2 is set to the second highest priority.

The priority is set by the DSP without passing through the bus.
Requests the bus arbiter 12 directly from 0. The bus access request and the bus access permission are transmitted between the DSP and the bus
It is exchanged directly between the arbiters 12 without going through a bus.
The permission to access the bus is output within one clock after the request to access the bus is input. By setting an arbitrary priority without using a bus, the throughput of the entire system can be improved.

While the embodiment of the present invention has been described above, the present invention can be implemented in other embodiments.
For example, when there are eight DSPs, as shown in FIG.
One DSP is set as one set, and two sets are set as one group. DSP0,1 is connected to the unit 0, DSP2,3 is connected to the unit 1, DSP4,5 is connected to the unit 2, and DSP6,7 is connected to the unit 3. Unit 0,
1 is connected to the unit 4 as one group, and the units 2 and 3 are connected to the unit 5 as one group. The units 4 and 5 are connected to the unit 6.

The selection of DSP0 and DSP1 is made by the signal S3,
The selection of SP2 and DSP3 is made by signal S4, and DSP4 and DSP3 are selected.
5 is a signal S5, and DSP6 and DSP7 are signals.
Perform each in S6. The selection of the units 0 and 1 is performed by the signal S1, the selection of the units 2 and 3 is performed by the signal S2, and the selection of the units 4 and 5 is performed by the signal S0.

While the invention has been described with reference to particular embodiments, the invention is not limited thereto.
The present invention can be practiced in various modified, modified, and modified modes based on the knowledge of those skilled in the art without departing from the spirit of the present invention. As long as the same action or effect occurs,
The present invention can be embodied in a form in which one of the invention specifying matters is replaced with another technique. The present invention can be embodied in a form in which the integrally formed invention specifying matter is constituted by a plurality of members, or in a form in which the invention specifying matter constituted by a plurality of members is integrally constituted.

[0041]

According to the present invention, a device for which access to the bus is permitted can be selected in an alternative manner by a signal specifying a priority. The device giving the highest priority can be arbitrarily changed. Regarding the priority other than the highest priority, any priority can be given to each device within an alternative range. It is possible to specify the priority order and give permission to access the bus without passing through the bus.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a bus arbitration system according to the present invention.

FIG. 2 is a block diagram showing a configuration example of a bus arbiter shown in FIG.

FIG. 3 is a block diagram showing a configuration example of units 0, 1, and 2 shown in FIG.

4 is a block diagram illustrating a configuration example of an interface for outputting a priority order designation signal of the DSP illustrated in FIG. 1;

FIG. 5 is a block diagram showing a configuration example of a unit B shown in FIG.

FIG. 6A is a diagram showing an outline of input of image data, and FIG. 6B is a diagram showing an example of data input for each line and a DSP for accessing a bus.

FIG. 7 is a block diagram illustrating a configuration example of a bus arbitration system according to the present invention targeting eight DSPs.

FIG. 8 is a block diagram illustrating a configuration example of a conventional bus arbitration system.

[Explanation of symbols]

 10: Bus arbitration system 12: Bus arbiter 14: FIFO memory 16: PCI bridge 20: Circuit for selecting an access request 22, 24, 42, 52: DFF 30: Unit 0, 1, 2 circuit 32: OR circuit 34 : AND circuit 36, 56: Inverter circuit 38: Alternative circuit 40: Output interface 50: Circuit of unit B 54: XOR circuit 60: Image 62: Line CCD 70: Conventional bus arbitration system 72: Conventional bus Arbiter

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Masahiko Kitagawa 800 Miyake-shi, Yasu-machi, Yasu-gun, Shiga Prefecture Inside the Yasu Office of IBM Japan, Ltd. 800 Miyake-shi, Japan IBM Japan, Ltd. Yasu Office (72) Inventor Yoshinobu Fukushima 800 Miyake, Yasu-cho, Yasu-gun, Shiga Prefecture IBM Japan, Ltd. Yasu Office F-term (reference) 5B045 AA01 EE03 EE13 EE33 5B060 CD12 5B061 BA01 BB16 GG15

Claims (12)

[Claims] 1. A plurality of devices connected to a common bus, priority specifying means for generating a signal for specifying a priority of access of the device to a bus, and a priority specifying means for each of the devices and the priority specifying means. Connected
A bus arbiter for granting access permission to any of the devices that have requested access to the bus in accordance with the signal designating the priority. 2. The bus arbiter, comprising two devices as one set, two input terminals to which access requests output from two devices are input for each set, and access permission to two devices. , A second output terminal for outputting an access request from one or both of the two devices, and an access request from one or both of the two devices based on the priority. The bus arbitration system according to claim 1, further comprising a second input terminal to which an access permission is input, and a third input terminal to which a signal for selecting one of access requests from two devices based on the priority order is input. . 3. The bus arbiter includes two input terminals to which two sets are grouped into one group, and for each group, two input terminals to which access requests from two sets of the second output terminals are input, respectively. Two output terminals for outputting access permission to the two sets of the second input terminals, a fourth output terminal for outputting an access request from one or both of the two sets, and one or two of the two sets In response to access requests from both, a fourth input terminal to which an access permission based on the priority is input, and a signal for selecting one of two sets of access requests based on the priority are input. 3. The bus arbitration system of claim 2, including a fifth input terminal. 4. The bus arbitration system according to claim 3, wherein when there are a plurality of groups, the two groups are further made into one group, and each group includes two groups or two sets. 5. The bus arbiter according to claim 1, wherein said bus arbiter includes a unit for aligning an input timing of an access request of each device, an input timing of a priority of each device, and an output timing of access permission to the device. Item 4. The bus arbitration system according to any one of Items 4. 6. A method for arbitrating access to a bus of a plurality of devices connected to a common bus, comprising the steps of specifying a priority of each device, and requesting access from each device to the bus. Selecting, from the devices that have requested access to the bus, a device to which access to the bus is permitted based on the priority order; and allowing the selected device to access the bus. Bus arbitration method. 7. The method according to claim 1, wherein the selecting step includes: setting two devices as a set; detecting an access request from one or both of the two devices for each set; 7. The bus arbitration method according to claim 6, further comprising: granting access to the access request based on the priority, and selecting one of the two devices based on the priority. 8. The step of selecting one of the two devices, when only one of the two devices is requesting access to the bus, selecting the device requesting access. Selecting the higher priority device when both devices are requesting access to the bus. 9. The method according to claim 9, wherein the selecting includes: setting the two sets as one group, and detecting, for each group, an access request to one or both of the two sets; and one or both of the two sets. Requests for access to
The bus arbitration method according to claim 7, further comprising: permitting access based on the priority; and selecting one of the two sets based on the priority. 10. A step of designating one of the two sets, when only one of the two sets has an access request to the bus, the step of designating the set having the access request. If there is a bus access request to
Specifying a set including the device with the highest priority. 11. The bus arbitration method according to claim 9, wherein when there are a plurality of groups, the two groups are further made into one group, and each group includes two groups or two sets. 12. Designating the priority order;
12. The bus arbitration method according to claim 6, wherein the step of requesting access to the bus and the step of permitting the access are performed simultaneously.