JPH0650499B2 - Data transfer method between microprocessors - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an inter-microprocessor data transfer system for performing data transfer between microprocessors using a common memory.

(Prior Art) FIG. 2 is a block diagram showing a conventional data transfer method using a common memory. In the figure, the common memory 22 temporarily stores the data of the microprocessors 23-1, 23-2, ..., 23-N and can be shared by the respective microprocessors. In addition, the common memory 22 and the microprocessors 23-1, 2
3-2, ..., 23-N are interconnected via a common bus 21.

Next, a conventional data transfer system having the above configuration will be described.

Microprocessor 23-1, 23-2, ..., 23-N is common memory 2
If you want to access 2, you can check if the common bus 21 is empty and use the microprocessor 23 until it becomes empty.
-1,23-2, ..., 23-N enters the waiting state. When the common bus 21 becomes empty, the waiting states of the microprocessors 23-1, 23-2, ..., 23-N are released and the microprocessors 23-1, 23-2 ,.
-N was accessing the common memory 22 via the common bus 21. For example, if the microprocessor 23-1
Microprocessor if you were accessing
When 23-2 desires to access the common memory 22, the microprocessor 23-2 waits until the access operation of the microprocessor 23-1 is completed, and the microprocessor 23-1
The common memory 22 can be accessed only after the access operation is completed.

(Problems to be Solved by the Invention) However, in the above conventional method, one of the microprocessors 23-1, 23-2, ..., 23-N is used as a central processing microprocessor having a high processing priority, and When is a distributed processing microprocessor, a wait state occurs in the central processing microprocessor even when the central processing microprocessor with a high processing priority transfers data to the distributed processing microprocessor. There is a problem that the processing capacity of the central processing microprocessor is reduced.

The present invention has been made to solve these problems and is intended for central processing depending on the waiting state of the central processing microprocessor, which occurs when the central processing microprocessor transfers data to the distributed processing microprocessor. It is an object of the present invention to provide a data transfer method between microprocessors capable of transferring data to a distributed processing microprocessor without lowering the processing capability of the microprocessor.

(Means for Solving Problems) In order to solve the above problems, a central processing microprocessor and a plurality of local distributed processing microprocessors are connected by a common bus in order to solve the above problems. In an inter-microprocessor data transfer method for transferring data between a central processing microprocessor and each local distributed processing microprocessor, an arithmetic processing unit, a common memory and access control means are provided in the local distributed processing microprocessor. There is a feature in that. Further, in detail, the arithmetic processing unit processes the data for distributed processing, and the common memory temporarily stores the data of the central processing microprocessor and the arithmetic processing unit. Further, the access control means puts the arithmetic processing unit in the waiting state in both cases of detecting an access operation to the common memory of the arithmetic processing unit and detecting an access operation to the common memory of the central processing microprocessor. The wait request signal is output to the arithmetic processing unit, and the wait request signal is released under the condition that the central processing microprocessor does not access the common memory. Further, the central processing microprocessor can access the common memory without waiting by the access control means regardless of whether or not the common memory of the arithmetic processing unit is accessed.

(Operation) In the central processing microprocessor, when accessing the common memory, the access control means outputs a wait request signal to the arithmetic processing unit in the local distributed processing microprocessor to put the arithmetic processing unit in the waiting state. Because
Common memory can be accessed with priority. Further, when the common memory is accessed in the arithmetic processing unit, the access control means temporarily puts it in a wait state, and releases the wait request signal after detecting that the central processing microprocessor is not accessing the common memory. To access the common memory.

Embodiment An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is a common bus, 2 is a central processing microprocessor, 3 is an arithmetic processing unit, 4 is a common memory, and 5 is a common memory.
Is a bus control circuit, 6 and 7 are bus gates, 8 is a local bus, 9 is a bus gate signal, 10 is a wait request signal, 11 is an inverter, 12-1, ..., 12-N are local distributed processing microprocessors. Is. Here, the arithmetic processing unit 3 has the same function as the distributed processing microprocessor in the conventional system. The common memory 4 is for temporarily storing the data of the central processing microprocessor 2 and the arithmetic processing unit 3. The bus control circuit 5 monitors whether or not the common bus 1 is empty, controls the bus gates 6 and 7 accordingly, and issues a wait state instruction to the arithmetic processing unit 3 to access the common memory 4. It is for controlling. Further, the bus control circuit 5 draws in the common bus 1 controlled by the central processing microprocessor 2 and the local bus 8 controlled by the arithmetic processing unit 3. Further, the bus gate signal 9 for controlling the common memory 4 is supplied to the enable terminal of the bus gate 6 and the enable terminal of the bus gate 7 through the inverter 11, and the wait request signal 10 for the arithmetic processing unit 3 is arithmetic processing. Part 3 WA
It is supplied to the IT terminal. Further, the common memory 4 is connected to the local bus 8 through the bus gate 6 and is connected to the common bus 1 through the bus gate 7.

Next, the operation of this embodiment will be described.

First, a local distributed processing microprocessor 12
-1, ..., 12-N is initially set to the bus control circuit 5
The output bus gate signal 9 is such that the bus gate 7 is enabled (logic "0" or "1") and the bus gate 6 is disabled (logic "1").
Alternatively, “0”) is set, and the central processing microprocessor 2 can access the common memory 4.

When the arithmetic processing unit 3 accesses the common memory 4, since the bus gate 6 is disabled by the above-described initialization, the bus control circuit 5 controls the access operation of the arithmetic processing unit 3 to the common memory 4. To detect. At that time, the bus control circuit 5 outputs a wait request signal 10 to the arithmetic processing unit 3 to put the arithmetic processing unit 3 in a waiting state. Then, it is detected that the central processing microprocessor 2 is accessing other than the common memory 4, the logic of the bus gate signal 9 is inverted, the bus gate 6 is enabled, the bus gate 7 is disabled, and the operation is performed. The output of the waiting request signal 10 of the processing unit 3 is stopped. That is, the bus control circuit 5 monitors the access status of the central processing microprocessor 2, and only when the central processing microprocessor 2 is accessing other than the common memory 4, the wait request signal 10 for the arithmetic processing unit 3 is received. Stop the output of. As a result, the arithmetic processing unit 3 goes out of the waiting state and accesses the common memory 4. Next, when the access to the common memory 4 of the arithmetic processing unit 3 is completed, the bus control circuit 5 restores the logic of the bus gate signal 9 to disable the bus gate 6 and enable the bus gate 7. As a result, the arithmetic processing unit 3
Access to the common memory 4 is completed.

However, even when the arithmetic processing unit 3 is accessing the common memory 4, when the central processing microprocessor 2 accesses the common memory 4, the bus control circuit 5 again sends a wait request signal to the arithmetic processing unit 3. 10 is output, the bus gate 7 is enabled, and the bus gate 6 is disabled. After that, the bus control circuit 5 continues to output the wait request signal 10 until the central processing microprocessor 2 accesses other than the common memory 4.

Further, the central processing microprocessor 2 has a common memory 4
, The bus gate 7 is previously enabled and the bus gate 6 is disabled when the arithmetic processing unit 3 is not accessing the common memory 4. Therefore, the central processing microprocessor 2 is in the waiting state. Can be accessed without. Furthermore, the arithmetic processing unit 3 uses the common memory 4
When the central processing microprocessor 2 accesses the common memory 4 when accessing the common memory 4, the bus control circuit 5 that detects the access of the central processing microprocessor 2 to the common memory 4 is processed by the arithmetic processing unit 3 A wait request signal is output to, the bus gate signal from the bus control circuit 5 enables the bus gate 7, and the bus gate 6 is disabled. Therefore, the arithmetic processing unit 3 which has received the wait request signal from the bus control circuit 5 enters the waiting state, and the central processing microprocessor 2 can access the waiting processing signal in the waiting state. The arithmetic processing unit 3 is the arithmetic processing unit 3
Waits until the access operation of the central processing microprocessor 2 is completed.

(Effect of the Invention) As described above, according to the present invention, when the data transfer between the microprocessors is performed between the central processing microprocessor and the distributed processing microprocessor, the common memory is provided on the distributed processing microprocessor. Thus, when the central control microprocessor accesses the common memory, it is possible to provide the inter-microprocessor data transfer method in which the common memory can be accessed without waiting and the processing capacity of the central processing microprocessor is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional data transfer system using a common memory. 1,21 ...... Common bus, 2 ...... Central processing microprocessor, 3 ...... Arithmetic processing unit, 4,22 ...... Common memory, 5 ...... Bus control circuit, 6, 7 ...... Bus gate, 8 ...... Local bus, 9 ... Bus gate signal, 10 ... Wait request signal, 11 ...
Inverter, 12-1 to 12-N ... Local distributed processing microprocessor, 23-1 to 23-N ... Microprocessor.

Claims (1)

[Claims] 1. A central processing microprocessor and a plurality of local distributed processing microprocessors are connected by a common bus, and the central processing microprocessor and each of the local distributed processing microprocessors are connected via the common bus. In an inter-microprocessor data transfer method for transferring data between processors, an arithmetic processing unit that processes distributed processing data in the local distributed processing microprocessor and receives a wait request signal and enters a waiting state A common memory for temporarily storing the central processing microprocessor and the arithmetic processing data; a case where an access operation to the common memory of the arithmetic processing unit is detected; and the common memory of the central processing microprocessor. The arithmetic processing unit in both cases when the access operation to the And a means for releasing the wait request signal on the condition that the central processing microprocessor does not access the common memory, while outputting a wait request signal for putting the A central processing microprocessor and access control means for controlling access to the communication memory from the arithmetic processing section are provided, regardless of whether the access control means accesses the common memory of the arithmetic processing section. A data transfer system between microprocessors, wherein the central processing microprocessor can access the common memory without waiting.