JPS6289157A - Data transfer system - Google Patents

Abstract

PURPOSE:To reduce a deterioration of a processing capacity of a central processing unit by deleting a bus occupying time during transferring the data between a main storage device and an input and output device while keeping an advantage of deleting the quantity of a hardware in a periphery of a bus circuit. CONSTITUTION:When the sequential data on a main storage address is transferred between an input and output device 41 and a main storage device 27, a data transfer control circuit 40 makes a central processing unit 23 stop using a bus through a bus priority control circuit 34, delivers the right of using a bus to the input and output device 41 and the data can be transferred between the device 41 and the main storage device 27. At this time, by changing over selector 39, 30 of an address counter 35, address buses 37, 31 are connected to an address bus 28 of the main storage device 27. After the transfer of the data is completed, the bus priority control circuit 34 progresses the address counter 35 by one and the right of using the bus of the input and output device 41 is opened. Thereby, a speed in transferring the data is improved, the deterioration in a processing capacity of the central processing unit is reduced and, which enables a slight data transfer.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer method, and more particularly to a data transfer method for transferring data between a main storage device and an input/output device in a single bus computer system.

[Conventional technology]

As shown in FIG. 2, a conventional computer system employing the bus system has a central processing unit 1, a main memory 5, and a bus control circuit 4.8. The address buses 2, 6 and data buses 3, 7 from are connected to a single bus 22 via a bus control circuit 4.8. Furthermore, this system includes a plurality of input/output devices 13.19, data transfer control circuits 10, 16 connected thereto, address counters 11.17 connected to each data transfer control circuit 10.16, and a bus control circuit 15.
．． 21, the address bus 12.18 connected to the address counter 11 and the data bus 14.20 connected to the input/output devices are bus control circuits 15.21, respectively.
is connected to a single bus 22 via. Note that the bus priority control circuit 9 is connected to the central processing unit 1 and a plurality of data transfer control circuits 10.16. In this conventional data transfer method for computer systems, address information must be transferred on the single bus 22 prior to data transfer when data is transferred between devices. Normally, data is constantly transferred between the central processing unit 1 and the main storage device 5 on the single bus 22 for program execution, but when an input/output request occurs, the input/output device 13 and the main storage device 5
When it becomes necessary to transfer continuous data on main memory addresses between
The CPU 1 causes the central processing unit 1 to stop using the bus and transfers the right to use the bus to the input/output device 13 to enable data transfer with the main storage device 5. Data transfer control circuit 10 connects address counter 11 to single bus 22 via address bus 12 and bus control circuit 15 . The bus control circuit 8 takes in the address counter value from the single bus 22, connects it to the address bus 6, and selects an address in the main memory 5. The bus control circuit 8.15 of both devices causes a single bus 22
By connecting the data bus 7.14 to the data bus 7.14, data transfer between the main storage device 5 and the input/output device 13 becomes possible. After the data transfer is completed, the data transfer control circuit 10 increments the address counter 11 by one and notifies the bus priority control circuit 9 that the right to use the bus has been released. Thereafter, the bus priority control circuit 9 grants the right to use the bus to one input/output device if there is a request to use the single bus 22 from the central processing unit 1 or the data transfer control circuit 16. The data transfer procedure between the turnout device 19 and the main storage device 5 is also the same as that between the input/output device 13 and the main storage device 5. Next, when an input/output request occurs to the input/output device 13 again, data transfer is performed in the same procedure as the previous time, but unlike before, the value of the address counter 11 has advanced by one, so that Address and data transfer becomes possible.

[Problem that the invention seeks to solve]

In the conventional data transfer method described above, transferring one piece of data between the input/output device and the main memory always consumes two bus cycles: an address transfer, a cycle data transfer cycle, and during this time the central processing unit If the system is stopped and input/output occurs frequently, the problem is that the performance of the central processing unit will deteriorate. In addition, as a way to solve this problem, the conventional data transfer method could be to send the address data once and then send it continuously while holding the data bus, but since the bus is not open for a long time, the central processing unit is This has disadvantages, such as the system stopping for a long time and cannot be used in systems that prohibit this.

The purpose of the present invention is to eliminate the drawbacks of conventional data transfer methods, and to transfer data between main storage devices and input/output devices while maintaining the advantage of reducing the amount of hardware around the bus circuit, which is a feature of the single bus method. An object of the present invention is to provide a data transfer method that reduces the reduction in the processing capacity of a central processing unit by reducing bus exclusive time. In a data transfer method in a single-bus computer system in which an address bus and a data bus are used as the same bus for data transfer in a time-sharing manner, a main storage device and an input/output device that transmit and receive continuous data, and An address counter is provided on the storage device side and for each input/output device and indicates address information in the main storage device, and when data is transferred between the main storage device side and the input/output device, data from the address counter is By obtaining the address information, the exclusive time of a single bus is limited to the time for transmitting data.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention. In FIG. 1, an embodiment of the present invention is a data transfer method of a single bus computer system, in which a central processing unit 23, a main storage device 27, A plurality of input/output devices 23, a main storage device 27,
A plurality of input/output devices 41.45 and each input/output device 40.4
A data transfer control circuit 40.44 connected to each data transfer control circuit 40.44, a bus priority control circuit 34 connected to each data transfer control circuit 40.44 and connected to the central processing unit 23, An address counter 35.36 provided for each of the plurality of input/output devices, a selector 39 connected to each address counter 35.36 via an address bus 37.38 and selecting this address counter 35.36, and a main memory device. and a selector 30 connected to 27.

The bus control circuit 26 includes an address bus 24 and a data bus 25.
The bus control circuit 33 is connected to the selector 30 via an address bus 32, and the main memory 27 via two data buses.
It is connected to the.

Further, the bus control circuits 43 and 47 each have a data bus 42.
．． 46 to input/output devices 41.45. These bus control circuits 26, 33, 43 and 47 are connected to a single bus 48.

As in the conventional system, a single bus 48 is used between the central processing unit 23 and the main memory 27 for constant program execution, and it takes an address transfer cycle and a data transfer cycle to send - times of data. Two bus cycles are used. When an input/output request occurs and continuous data is transferred between the input/output device 41 and the main memory device 27 at the main memory address, the data transfer control circuit 40 uses the bus priority control circuit 34
The central processing unit 23 is made to stop using the bus, and the right to use the bus is passed to the input/output device 41 to enable data transfer with the main storage device 27. At this time, the bus priority control circuit 34 selects the address bus 37 . Connect via 31. Main storage device 2
The bus control circuit 33 of 7 connects the single bus 48 and the data bus 29 to the two data bus sides, thereby enabling data transfer between the main storage device 27 and the input/output device 41. After the data transfer is completed, the bus priority control circuit 34 starts the address counter 3.
5 is advanced by one, and the bus usage right of the input/output device 41 is released. After that, the bus priority control circuit 34 causes the central processing unit 23 to
Alternatively, if there is a request to use the single bus 48 from the data transfer control circuit 44, the input/output device 45 is given the right to use the bus. The data transfer procedure between the input/output bag m45 and the main storage device 27 is also the same as that for the input/output device 41. However, in this case, the address information is obtained from the address counter 36 installed for each input/output device.Next, when an input/output request occurs again to the input/output device 41, data transfer is performed using the same procedure as last time, but unlike the previous one, The value of the address counter 35 advances by one, thus making it possible to transfer data at consecutive addresses within the main memory 27. In this way, in this embodiment, two bus cycles, an address transfer cycle and a data transfer cycle, are always used to transfer one data between the input/output device and the main memory device, whereas in the conventional method, two bus cycles, an address transfer cycle and a data transfer cycle, are used. This is done in one bus cycle. Furthermore, in this embodiment, the single bus usage rate for data transfer between the input/output device and the main memory device is halved, resulting in an improvement in bus transfer speed or a decrease in processing capacity due to the bus waiting time of the central processing unit. can be prevented.

〔Effect of the invention〕

As explained above, according to the present invention, data transfer time can be halved by providing a memory counter on the main storage side, and the data transfer speed can be improved or the processing capacity of the central processing unit may be slightly reduced. Transfer becomes possible. Regarding the amount of hardware required to realize the data transfer method according to the present invention, the address counter that was conventionally located on the data transfer control circuit side has been moved to the main storage device side, and the selector for switching the memory counter for each input/output device has been changed from the conventional method. Since it extracts the functions included in the bus control circuit of the input/output device, it can be implemented on almost the same scale as the conventional system, and it is possible to secure the economy that is a characteristic of the single bus system.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a data transfer method in a single bus computer system according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a data transfer method in a conventional single bus computer system. be. 1.23...Central processing unit, 2,6.12,18°2
4.28.31.32.37.38...address bus, 3.7.14.20.25.29.42゜46...
Data bus, 4, 8, 15, 21.26° 3B, 4.3
．． 47... Bus control circuit, 5.27. ... Main memory device, 9.34 ... Bus end control circuit, 10°16.4
0.44...Data transfer control circuit, 11°17.35
．． 36...Address counter, 13.19.41.4
5...I/O device, 22.48...Single bus, 30
．． 39...Selector.

Claims (1)

[Claims] In a data transfer method in a single-bus computer system in which an address bus, a data bus, and the same bus are used in a time-sharing manner for data transfer between devices, a main storage device and input/output that transmit and receive continuous data; An address counter is provided on the main storage device side and for each input/output device and indicates address information in the main storage device, and when data is transferred between the main storage device side and the input/output device, data from the address counter is A data transfer method characterized in that by obtaining address information, the exclusive time of a single bus is limited to the time for transmitting data.