JPS61235951A - One chip microcomputer - Google Patents

Abstract

PURPOSE:To shorten the processing time of after an interruption has been generated, by providing an interruption processing table selecting flag having information for selecting one of a data memory part and an interruption vector address. CONSTITUTION:A data memory part 11 and a program memory part 12 have an interruption vector address. An interruption processing table selecting flag 13 has information for selecting an interruption vector address of one of the data memory part 11 and the program memory part 12. An interruption permitting flag 14 has information of a permission or an inhibition to a processing of the time when an interruption has been generated, and if the interruption is generated at the time of a state that the interruption is inhibited, the processing is reserved until the interruption is permitted. With respect to the generation of the interruption from an interruption factor, an interruption controlling circuit 15 refers to the interruption vector address of the data memory part 11 or the program memory part 12 by the interruption processing table selecting flag 13 and the interruption permitting flag 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a one-chip microcomputer with an interrupt function.

[Conventional technology]

Conventionally, the interrupt function of a one-chip microcomputer has a table that is processed only in the program memory section (R, OM) when an interrupt occurs (hereinafter referred to as a side input vector address) was placed there.

[Problem that the invention seeks to solve]

With conventional interrupt functions, when an interrupt occurs, it is always processed from the same address. Therefore, when an interrupt occurs from one interrupt source and all processes with different contents are performed, all processes necessary to branch to each process are required after the interrupt occurs. The drawback is that the processing time is longer.

[Means for solving problems]

The interrupt function of the present invention has the interrupt vector address set to 7'.
The interrupt processing table selection also has information on which of the interrupt vector addresses stored in the data memory section and the program memory section are to be selected. Flag 'L[
do.

[Example] - Next, the present invention will be explained with reference to the drawings.

FIGS. 1 and 2 are block diagrams of an embodiment of the present invention. Data memory section 11 and program memory section 12 have interrupt vector addresses. The interrupt processing table selection 7 lag 13 has information as to which interrupt vector address in the data memory section 11 or the program memory section 12 is to be selected. The interrupt permission flag 14 has information indicating whether processing is permitted or prohibited when an interrupt occurs, and if an interrupt occurs while the interrupt is prohibited, the interrupt is suspended until the interrupt is permitted. The interrupt control circuit 15 refers to all interrupt vector addresses in the data memory section 11 or the program memory section 12 using the interrupt processing table selection flag 13 and the interrupt enable 7 flag 14 in response to the occurrence of an interrupt from an interrupt cause. In this way, the one-chip microcombiator 21 having the data memory section 11, the program memory section 121, the interrupt processing table selection flag 13, the interrupt permission flag 141, and the interrupt control section 15 receives an interrupt from the interrupt signal generation factors 21, 22, and 23. is applied.

When power is applied to the circuit shown in the block diagram shown in Figure 2,
Interrupt processing table selection flag 13 is set by the reset signal.
When an interrupt occurs, information is written so that the interrupt vector address in the program memory unit 12 is referenced. At this time, when an interrupt is generated by the interrupt signal generation factor 21, all interrupt vector addresses in the program memory unit 12 are referenced. Next, as the execution of the program progresses and an interrupt starts to be generated from the interrupt signal generation factor 22, interrupts are enabled and disabled, and all the data is stored at the interrupt vector address in the data memory section 11. At the same time as writing, the interrupt handler address of the data memory section 11 is referred to in the interrupt processing table selection flag 13, the information sound 11 is written, and the interrupt permission flag 14 is set to an interrupt permission state. At this time, when an interrupt is generated by the interrupt signal generation factor 22, the interrupt vector address in the data memory section 11 is referred to. Furthermore, as the execution of the program progresses, when an interrupt occurs from the interrupt signal generation factor 23, all interrupts are set to the interrupt enable 7 lag 14 state, and the interrupt vector address of the data memory section 11 is set to the interrupt signal generation factor 23. t-th data t-write, interrupt permission flag 14, set to interrupt permission state.

At this time, when an interrupt is generated by the interrupt signal generation factor 23, the newly written interrupt vector address in the data memory section 11 is referred to.

〔Effect of the invention〕

As explained above and as follows, the interrupt function of the present invention has an interrupt vector address stored in the data memory section, so that the interrupt function can be used to respond to an interrupt generated from one interrupt factor before the interrupt occurs. Processing of several different contents
- It has the effect of allowing settings and changes, and the effect of simplifying the processing contents and shortening the processing time after an interrupt occurs.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a part related to the invention of a chip micro combinator according to an embodiment of the present invention, and FIG. 2 is a block diagram of a system using a chip micro combinator according to an embodiment of the present invention. be. 11...Data memory section, 12...Program...
Memory section, 13... Interrupt processing table selection flag,
14... Interrupt permission flag, 15... Interrupt control circuit, 16... Reset signal, 17... Interrupt factor,
18...Program counter, 19...Central processing unit, 10...Bus, 21...One-chip micro combiator, 22.23.24...Interrupt signal generation factor 11: Daemono Shichisogu 12 Nibrogram, meshichiso part 13; sideman world processing table lotus flag 14: wealth crawling ox language 7 lag + 5: t entry J to system #C fu 1 @- 16; lyse, 7 toy language 17: Official h$51 1S: Pro 2゛U4. Counter 19; Central processing unit 10: High speed

Claims (1)

[Claims] A data memory section that has a table that is processed when an interrupt occurs, a program memory section that has a table that is processed when an interrupt occurs, an interrupt processing table selection flag, a control section that generates an interrupt processing address, and an interrupt enable flag. A one-chip microcomputer characterized by: